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| author | Segher Boessenkool <segher@kernel.crashing.org> | 2016-11-21 23:29:34 +0100 |
|---|---|---|
| committer | Segher Boessenkool <segher@gcc.gnu.org> | 2016-11-21 23:29:34 +0100 |
| commit | d8fc036893ff96464d5dd5767a97348a9a4f327c (patch) | |
| tree | f0452348a7d1c0cc2f02448bd24df5a48f1cc3f0 /gcc | |
| parent | d85e598a59f826d0fbd4af684c680b68970e6cda (diff) | |
| download | gcc-d8fc036893ff96464d5dd5767a97348a9a4f327c.zip gcc-d8fc036893ff96464d5dd5767a97348a9a4f327c.tar.gz gcc-d8fc036893ff96464d5dd5767a97348a9a4f327c.tar.bz2 | |
rs6000: rl[wd]imi without shift/rotate (PR68803)
We didn't have patterns yet for rl[wd]imi insns that do a rotate by 0.
This fixes it.
PR target/68803
* config/rs6000/rs6000.md (*rotlsi3_insert_5, *rotldi3_insert_6,
*rotldi3_insert_7): New define_insns.
From-SVN: r242681
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 44 |
2 files changed, 50 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 842e8ff..41772a0 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2016-11-21 Segher Boessenkool <segher@kernel.crashing.org> + + PR target/68803 + * config/rs6000/rs6000.md (*rotlsi3_insert_5, *rotldi3_insert_6, + *rotldi3_insert_7): New define_insns. + 2016-11-21 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/rs6000.md (movdi_internal32): Change constraints diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index c932dac..f3d1d715 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -3853,6 +3853,50 @@ } [(set_attr "type" "insert")]) +(define_insn "*rotlsi3_insert_5" + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (ior:SI (and:SI (match_operand:SI 1 "gpc_reg_operand" "0,r") + (match_operand:SI 2 "const_int_operand" "n,n")) + (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,0") + (match_operand:SI 4 "const_int_operand" "n,n"))))] + "rs6000_is_valid_mask (operands[2], NULL, NULL, SImode) + && UINTVAL (operands[2]) != 0 && UINTVAL (operands[4]) != 0 + && UINTVAL (operands[2]) + UINTVAL (operands[4]) + 1 == 0" + "@ + rlwimi %0,%3,0,%4 + rlwimi %0,%1,0,%2" + [(set_attr "type" "insert")]) + +(define_insn "*rotldi3_insert_6" + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") + (ior:DI (and:DI (match_operand:DI 1 "gpc_reg_operand" "0") + (match_operand:DI 2 "const_int_operand" "n")) + (and:DI (match_operand:DI 3 "gpc_reg_operand" "r") + (match_operand:DI 4 "const_int_operand" "n"))))] + "exact_log2 (-UINTVAL (operands[2])) > 0 + && UINTVAL (operands[2]) + UINTVAL (operands[4]) + 1 == 0" +{ + operands[5] = GEN_INT (64 - exact_log2 (-UINTVAL (operands[2]))); + return "rldimi %0,%3,0,%5"; +} + [(set_attr "type" "insert") + (set_attr "size" "64")]) + +(define_insn "*rotldi3_insert_7" + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") + (ior:DI (and:DI (match_operand:DI 3 "gpc_reg_operand" "r") + (match_operand:DI 4 "const_int_operand" "n")) + (and:DI (match_operand:DI 1 "gpc_reg_operand" "0") + (match_operand:DI 2 "const_int_operand" "n"))))] + "exact_log2 (-UINTVAL (operands[2])) > 0 + && UINTVAL (operands[2]) + UINTVAL (operands[4]) + 1 == 0" +{ + operands[5] = GEN_INT (64 - exact_log2 (-UINTVAL (operands[2]))); + return "rldimi %0,%3,0,%5"; +} + [(set_attr "type" "insert") + (set_attr "size" "64")]) + ; This handles the important case of multiple-precision shifts. There is ; no canonicalization rule for ASHIFT vs. LSHIFTRT, so two patterns. |