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| author | Michael Meissner <meissner@linux.vnet.ibm.com> | 2016-11-21 20:35:21 +0000 |
|---|---|---|
| committer | Michael Meissner <meissner@gcc.gnu.org> | 2016-11-21 20:35:21 +0000 |
| commit | d85e598a59f826d0fbd4af684c680b68970e6cda (patch) | |
| tree | 66b37a5fdb0f33b31a0b7685fee5fb8fbc0a964d /gcc | |
| parent | 699e8cb7b4d067cabff5a92bdbbb2d0d0dddc262 (diff) | |
| download | gcc-d85e598a59f826d0fbd4af684c680b68970e6cda.zip gcc-d85e598a59f826d0fbd4af684c680b68970e6cda.tar.gz gcc-d85e598a59f826d0fbd4af684c680b68970e6cda.tar.bz2 | |
rs6000.md (movdi_internal32): Change constraints so that DImode can be allocated to FP/vector registers in...
[gcc]
2016-11-21 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000.md (movdi_internal32): Change constraints
so that DImode can be allocated to FP/vector registers in more
cases, and we can avoid direct move operations. If the register
needs reloading, prefer GPRs over FP/vector registers. In the
case of FPR vs. Altivec registers, prefer FPR registers unless we
have the ISA 3.0 reg+offset scalar instructions.
(movdi_internal64): Likewise.
[gcc/testsuite]
2016-11-21 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/ppc-round2.c: Allow XSCVDPSXWS and XSCVDPUXWS
to be generated instead of FCTIWUZ or FCTIWZ.
From-SVN: r242679
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 10 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 14 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/powerpc/ppc-round2.c | 4 |
4 files changed, 24 insertions, 9 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9cb2526..842e8ff 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2016-11-21 Michael Meissner <meissner@linux.vnet.ibm.com> + + * config/rs6000/rs6000.md (movdi_internal32): Change constraints + so that DImode can be allocated to FP/vector registers in more + cases, and we can avoid direct move operations. If the register + needs reloading, prefer GPRs over FP/vector registers. In the + case of FPR vs. Altivec registers, prefer FPR registers unless we + have the ISA 3.0 reg+offset scalar instructions. + (movdi_internal64): Likewise. + 2016-11-21 Jakub Jelinek <jakub@redhat.com> PR middle-end/67335 diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index acd4a7e..c932dac 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -8118,10 +8118,10 @@ (define_insn "*movdi_internal32" [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" - "=Y, r, r, ?m, ?*d, ?*d, - r, ?wY, ?Z, ?*wb, ?*wv, ?wi, - ?wo, ?wo, ?wv, ?wi, ?wi, ?wv, - ?wv") + "=Y, r, r, ^m, ^d, ^d, + r, ^wY, $Z, ^wb, $wv, ^wi, + *wo, *wo, *wv, *wi, *wi, *wv, + *wv") (match_operand:DI 1 "input_operand" "r, Y, r, d, m, d, @@ -8195,9 +8195,9 @@ (define_insn "*movdi_internal64" [(set (match_operand:DI 0 "nonimmediate_operand" "=Y, r, r, r, r, r, - ?m, ?*d, ?*d, ?wY, ?Z, ?*wb, - ?*wv, ?wi, ?wo, ?wo, ?wv, ?wi, - ?wi, ?wv, ?wv, r, *h, *h, + ^m, ^d, ^d, ^Y, $Z, $wb, + $wv, ^wi, *wo, *wo, *wv, *wi, + *wi, *wv, *wv, r, *h, *h, ?*r, ?*wg, ?*r, ?*wj") (match_operand:DI 1 "input_operand" diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index dd89d88..cef6a27 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2016-11-21 Michael Meissner <meissner@linux.vnet.ibm.com> + + * gcc.target/powerpc/ppc-round2.c: Allow XSCVDPSXWS and XSCVDPUXWS + to be generated instead of FCTIWUZ or FCTIWZ. + 2016-11-21 Jakub Jelinek <jakub@redhat.com> PR middle-end/67335 diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-round2.c b/gcc/testsuite/gcc.target/powerpc/ppc-round2.c index 39375a0..1890fca 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-round2.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-round2.c @@ -5,8 +5,8 @@ /* { dg-options "-O2 -mcpu=power8" } */ /* { dg-final { scan-assembler-times "fcfid " 2 } } */ /* { dg-final { scan-assembler-times "fcfids " 2 } } */ -/* { dg-final { scan-assembler-times "fctiwuz " 2 } } */ -/* { dg-final { scan-assembler-times "fctiwz " 2 } } */ +/* { dg-final { scan-assembler-times "fctiwuz \|xscvdpuxws " 2 } } */ +/* { dg-final { scan-assembler-times "fctiwz \|xscvdpsxws " 2 } } */ /* { dg-final { scan-assembler-times "mfvsrd " 4 } } */ /* { dg-final { scan-assembler-times "mtvsrwa " 2 } } */ /* { dg-final { scan-assembler-times "mtvsrwz " 2 } } */ |