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| author | David Edelsohn <edelsohn@gnu.org> | 2005-07-09 01:13:03 +0000 |
|---|---|---|
| committer | David Edelsohn <dje@gcc.gnu.org> | 2005-07-08 21:13:03 -0400 |
| commit | d54c47e1b5334835cf39591618991d34f51ce8c0 (patch) | |
| tree | efa59b788fe2e584d7ef67ab924ae090dad17200 /gcc | |
| parent | c00fc5cf8b1979cd4a9200ec05593f2dba9f1eb0 (diff) | |
| download | gcc-d54c47e1b5334835cf39591618991d34f51ce8c0.zip gcc-d54c47e1b5334835cf39591618991d34f51ce8c0.tar.gz gcc-d54c47e1b5334835cf39591618991d34f51ce8c0.tar.bz2 | |
sync.md (load_locked_<mode>): Use Z for memory_operand constraint.
* config/rs6000/sync.md (load_locked_<mode>): Use Z for
memory_operand constraint.
(store_conditional_<mode>): Same.
(sync_compare_and_swap<mode>): Same.
(sync_lock_test_and_set<mode>): Same.
From-SVN: r101813
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/config/rs6000/sync.md | 8 |
2 files changed, 12 insertions, 4 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6c5e2bb..ed5f975 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2005-07-08 David Edelsohn <edelsohn@gnu.org> + + * config/rs6000/sync.md (load_locked_<mode>): Use Z for + memory_operand constraint. + (store_conditional_<mode>): Same. + (sync_compare_and_swap<mode>): Same. + (sync_lock_test_and_set<mode>): Same. + 2005-07-08 Hans-Peter Nilsson <hp@axis.com> Rewrite PIC support to more closely model actual instructions. diff --git a/gcc/config/rs6000/sync.md b/gcc/config/rs6000/sync.md index a98dc15..cef6478 100644 --- a/gcc/config/rs6000/sync.md +++ b/gcc/config/rs6000/sync.md @@ -41,7 +41,7 @@ (define_insn "load_locked_<mode>" [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") (unspec_volatile:GPR - [(match_operand:GPR 1 "memory_operand" "m")] UNSPECV_LL))] + [(match_operand:GPR 1 "memory_operand" "Z")] UNSPECV_LL))] "TARGET_POWERPC" "<larx> %0,%y1" [(set_attr "type" "load_l")]) @@ -49,7 +49,7 @@ (define_insn "store_conditional_<mode>" [(set (match_operand:CC 0 "cc_reg_operand" "=x") (unspec_volatile:CC [(const_int 0)] UNSPECV_SC)) - (set (match_operand:GPR 1 "memory_operand" "=m") + (set (match_operand:GPR 1 "memory_operand" "=Z") (match_operand:GPR 2 "gpc_reg_operand" "r"))] "TARGET_POWERPC" "<stcx> %2,%y1" @@ -57,7 +57,7 @@ (define_insn_and_split "sync_compare_and_swap<mode>" [(set (match_operand:GPR 0 "gpc_reg_operand" "=&r") - (match_operand:GPR 1 "memory_operand" "+m")) + (match_operand:GPR 1 "memory_operand" "+Z")) (set (match_dup 1) (unspec_volatile:GPR [(match_operand:GPR 2 "reg_or_short_operand" "rI") @@ -77,7 +77,7 @@ (define_insn_and_split "sync_lock_test_and_set<mode>" [(set (match_operand:GPR 0 "gpc_reg_operand" "=&r") - (match_operand:GPR 1 "memory_operand" "+m")) + (match_operand:GPR 1 "memory_operand" "+Z")) (set (match_dup 1) (unspec_volatile:GPR [(match_operand:GPR 2 "reg_or_short_operand" "rL")] |