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| author | Kyrylo Tkachov <kyrylo.tkachov@arm.com> | 2020-09-22 12:00:38 +0100 |
|---|---|---|
| committer | Kyrylo Tkachov <kyrylo.tkachov@arm.com> | 2020-09-22 12:00:38 +0100 |
| commit | d4703be185b422f637deebd3bb9222a41c8023d6 (patch) | |
| tree | 8bdead459e0e8a5281254bcf86d977509d657f1f /gcc | |
| parent | fa9ad35dae03dcb20c4ccb50ba1b351a8ab77970 (diff) | |
| download | gcc-d4703be185b422f637deebd3bb9222a41c8023d6.zip gcc-d4703be185b422f637deebd3bb9222a41c8023d6.tar.gz gcc-d4703be185b422f637deebd3bb9222a41c8023d6.tar.bz2 | |
AArch64: Implement missing vceq*_p* intrinsics
This patch implements some missing vceq* intrinsics on poly types.
The behaviour is to produce the appropriate CMEQ instruction as for the unsigned types.
Bootstrapped and tested on aarch64-none-linux-gnu.
gcc/
PR target/71233
* config/aarch64/arm_neon.h (vceqq_p64, vceqz_p64, vceqzq_p64): Define.
gcc/testsuite/
PR target/71233
* gcc.target/aarch64/simd/vceq_poly_1.c: New test.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/aarch64/arm_neon.h | 21 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/simd/vceq_poly_1.c | 29 |
2 files changed, 50 insertions, 0 deletions
diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index 81cabb2..caeba10 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -12670,6 +12670,13 @@ vceqq_u64 (uint64x2_t __a, uint64x2_t __b) return (__a == __b); } +__extension__ extern __inline uint64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vceqq_p64 (poly64x2_t __a, poly64x2_t __b) +{ + return (__a == __b); +} + /* vceq - scalar. */ __extension__ extern __inline uint32_t @@ -12779,6 +12786,13 @@ vceqz_u64 (uint64x1_t __a) return (__a == __AARCH64_UINT64_C (0)); } +__extension__ extern __inline uint64x1_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vceqz_p64 (poly64x1_t __a) +{ + return (__a == __AARCH64_UINT64_C (0)); +} + __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vceqzq_f32 (float32x4_t __a) @@ -12856,6 +12870,13 @@ vceqzq_u64 (uint64x2_t __a) return (__a == __AARCH64_UINT64_C (0)); } +__extension__ extern __inline uint64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vceqzq_p64 (poly64x2_t __a) +{ + return (__a == __AARCH64_UINT64_C (0)); +} + /* vceqz - scalar. */ __extension__ extern __inline uint32_t diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vceq_poly_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vceq_poly_1.c new file mode 100644 index 0000000..7d43352 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vceq_poly_1.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-O" } */ + +#include <arm_neon.h> + +uint64x2_t +foo (poly64x2_t a, poly64x2_t b) +{ + return vceqq_p64 (a, b); +} + +/* { dg-final { scan-assembler-times "cmeq\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d" 1 } } */ + +uint64x1_t +fooz (poly64x1_t a) +{ + return vceqz_p64 (a); +} + +/* { dg-final { scan-assembler-times "cmeq\\td\[0-9\]+, d\[0-9\]+, #0" 1 } } */ + +uint64x2_t +fooqz (poly64x2_t a) +{ + return vceqzq_p64 (a); +} + +/* { dg-final { scan-assembler-times "cmeq\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, #0" 1 } } */ + |