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authorRichard Earnshaw <rearnsha@arm.com>1999-02-16 11:00:47 +0000
committerRichard Earnshaw <rearnsha@gcc.gnu.org>1999-02-16 11:00:47 +0000
commitd2ceebd171b3c9dc2d6079ca8e49012d2f0dd21c (patch)
treef6629bf735ba63b605e454db45988851d4c945c3 /gcc
parente84aaeeb5e1652dc24df45574c765e013a0f84a7 (diff)
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arm.md (*zeroextractqi_compare0_scratch): Re-add load instruction killed in previous change.
* config/arm/arm.md (*zeroextractqi_compare0_scratch): Re-add load instruction killed in previous change. Simplify mask generation. (*zeroextractsi_compare0_scratch): Simpify mask generation. From-SVN: r25241
Diffstat (limited to 'gcc')
-rw-r--r--gcc/ChangeLog6
-rw-r--r--gcc/config/arm/arm.md25
2 files changed, 13 insertions, 18 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 98e194f..0b6bbdf 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+Tue Feb 16 10:53:51 1999 Richard Earnshaw (rearnsha@arm.com)
+
+ * config/arm/arm.md (*zeroextractqi_compare0_scratch): Re-add load
+ instruction killed in previous change. Simplify mask generation.
+ (*zeroextractsi_compare0_scratch): Simpify mask generation.
+
Tue Feb 16 09:52:26 1999 Nick Clifton <nickc@cygnus.com>
* config/arm/arm.md (zeroextractqi_compare0_scratch): Ensure that
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index b9241c8..cf4212b 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -1193,16 +1193,10 @@
&& INTVAL (operands[1]) + (INTVAL (operands[2]) & 1) <= 8
&& INTVAL (operands[1]) + INTVAL (operands[2]) <= 32"
"*
-{
- unsigned int mask = 0;
- int cnt = INTVAL (operands[1]);
-
- while (cnt--)
- mask = (mask << 1) | 1;
- operands[1] = GEN_INT (mask << INTVAL (operands[2]));
+ operands[1] = GEN_INT (((1 << INTVAL (operands[1])) - 1)
+ << INTVAL (operands[2]));
output_asm_insn (\"tst%?\\t%0, %1\", operands);
return \"\";
-}
"
[(set_attr "conds" "set")])
@@ -1214,19 +1208,14 @@
(match_operand 2 "const_int_operand" "n"))
(const_int 0)))
(clobber (match_scratch:QI 3 "=r"))]
- "INTVAL (operands[2]) >= 0 && INTVAL (operands[1]) > 0 &&
- ((INTVAL (operands[1]) + INTVAL (operands[2])) <= 8)"
+ "INTVAL (operands[2]) >= 0 && INTVAL (operands[1]) > 0
+ && (INTVAL (operands[2]) + INTVAL (operands[1]) <= 8)"
"*
-{
- unsigned int mask = 0;
- int cnt = INTVAL (operands[1]);
-
- while (cnt--)
- mask = (mask << 1) | 1;
- operands[1] = GEN_INT (mask << INTVAL (operands[2]));
+ operands[1] = GEN_INT (((1 << INTVAL (operands[1])) - 1)
+ << INTVAL (operands[2]));
+ output_asm_insn (\"ldr%?b\\t%3, %0\", operands);
output_asm_insn (\"tst%?\\t%3, %1\", operands);
return \"\";
-}
"
[(set_attr "conds" "set")
(set_attr "length" "8")])