24k.md (r24k_unknown_store): Delete special handling for cprestore.

2012-08-06  Sandra Loosemore  <sandra@codesourcery.com>
	    Maxim Kuvyrkov  <maxim@codesourcery.com>
	    Julian Brown  <julian@codesourcery.com>

	gcc/
	* config/mips/24k.md (r24k_unknown_store): Delete special handling
	for cprestore.
	(r24k_int_load, r24k_int_arith, r24k_int_mul3, r24k_int_mfhilo)
	(r24k_int_cop, r24k_int_multi)
	(r24kf2_1_fcvt_f2i, r24kf2_1_fxfer)
	(r24kf1_1_fcvt_f2i, r24kf1_1_fxfer): Use mips_store_data_bypass_p
	instead of store_data_bypass_p.
	* config/mips/74k.md (r74k_int_store): Delete special handling for
	cprestore.
	(r74k_int_load, r74k_int_logical, r74k_int_arith, r74k_int_cmove):
	Use mips_store_data_bypass_p instead of store_data_bypass_p.

Co-Authored-By: Julian Brown <julian@codesourcery.com>
Co-Authored-By: Maxim Kuvyrkov <maxim@codesourcery.com>

From-SVN: r190189

3 files changed, 38 insertions, 28 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 26e3e0f..1aa0e5e 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,19 @@
+2012-08-06  Sandra Loosemore  <sandra@codesourcery.com>
+	    Maxim Kuvyrkov  <maxim@codesourcery.com>
+	    Julian Brown  <julian@codesourcery.com>
+
+	* config/mips/24k.md (r24k_unknown_store): Delete special handling
+	for cprestore.
+	(r24k_int_load, r24k_int_arith, r24k_int_mul3, r24k_int_mfhilo)
+	(r24k_int_cop, r24k_int_multi)
+	(r24kf2_1_fcvt_f2i, r24kf2_1_fxfer)
+	(r24kf1_1_fcvt_f2i, r24kf1_1_fxfer): Use mips_store_data_bypass_p
+	instead of store_data_bypass_p.
+	* config/mips/74k.md (r74k_int_store): Delete special handling for
+	cprestore.
+	(r74k_int_load, r74k_int_logical, r74k_int_arith, r74k_int_cmove):
+	Use mips_store_data_bypass_p instead of store_data_bypass_p.
+
 2012-08-06  Marc Glisse  <marc.glisse@inria.fr>
 
 	PR tree-optimization/51938
diff --git a/gcc/config/mips/24k.md b/gcc/config/mips/24k.md
index bc4b45b..72ae683 100644
--- a/gcc/config/mips/24k.md
+++ b/gcc/config/mips/24k.md
@@ -122,18 +122,7 @@
 ;; 6. Store
 (define_insn_reservation "r24k_int_store" 1
   (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
-       (and (eq_attr "type" "store")
-	    (eq_attr "mode" "!unknown")))
-  "r24k_iss+r24k_ixu_arith")
-
-;; 6.1 Special case - matches the cprestore pattern which don't set the mode
-;;     attrib. This avoids being set as r24k_int_store and have it checked
-;;     against store_data_bypass_p, which would then fail because cprestore
-;;     does not have a normal SET pattern.
-(define_insn_reservation "r24k_unknown_store" 1
-  (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
-       (and (eq_attr "type" "store")
-	    (eq_attr "mode" "unknown")))
+       (eq_attr "type" "store"))
   "r24k_iss+r24k_ixu_arith")
 
 
@@ -169,7 +158,7 @@
 ;; load->store base: 3 cycles
 ;; load->prefetch:   3 cycles
 (define_bypass 3 "r24k_int_load" "r24k_int_load")
-(define_bypass 3 "r24k_int_load" "r24k_int_store" "!store_data_bypass_p")
+(define_bypass 3 "r24k_int_load" "r24k_int_store" "!mips_store_data_bypass_p")
 (define_bypass 3 "r24k_int_load" "r24k_int_prefetch")
 
 ;; arith->next use :  1 cycles (Default)
@@ -177,14 +166,14 @@
 ;; arith->store base: 2 cycles
 ;; arith->prefetch:   2 cycles
 (define_bypass 2 "r24k_int_arith" "r24k_int_load")
-(define_bypass 2 "r24k_int_arith" "r24k_int_store" "!store_data_bypass_p")
+(define_bypass 2 "r24k_int_arith" "r24k_int_store" "!mips_store_data_bypass_p")
 (define_bypass 2 "r24k_int_arith" "r24k_int_prefetch")
 
 ;; mul3->next use : 5 cycles (default)
 ;; mul3->l/s base : 6 cycles
 ;; mul3->prefetch : 6 cycles
 (define_bypass 6 "r24k_int_mul3" "r24k_int_load")
-(define_bypass 6 "r24k_int_mul3" "r24k_int_store" "!store_data_bypass_p")
+(define_bypass 6 "r24k_int_mul3" "r24k_int_store" "!mips_store_data_bypass_p")
 (define_bypass 6 "r24k_int_mul3" "r24k_int_prefetch")
 
 ;; mul3->madd/msub : 1 cycle
@@ -195,20 +184,22 @@
 ;; mfhilo->prefetch  : 6 cycles
 ;; mthilo->madd/msub : 2 cycle (only for mthi/lo not mfhi/lo)
 (define_bypass 6 "r24k_int_mfhilo" "r24k_int_load")
-(define_bypass 6 "r24k_int_mfhilo" "r24k_int_store" "!store_data_bypass_p")
+(define_bypass 6 "r24k_int_mfhilo" "r24k_int_store"
+  "!mips_store_data_bypass_p")
 (define_bypass 6 "r24k_int_mfhilo" "r24k_int_prefetch")
 (define_bypass 2 "r24k_int_mthilo" "r24k_int_madd")
 
 ;; cop->next use : 3 cycles (Default)
 ;; cop->l/s base : 4 cycles
 ;; (define_bypass 4 "r24k_int_cop" "r24k_int_load")
-;; (define_bypass 4 "r24k_int_cop" "r24k_int_store" "!store_data_bypass_p")
+;; (define_bypass 4 "r24k_int_cop" "r24k_int_store"
+;;   "!mips_store_data_bypass_p")
 
 ;; multi->next use : 1 cycles (Default)
 ;; multi->l/s base : 2 cycles
 ;; multi->prefetch : 2 cycles
 (define_bypass 2 "r24k_int_multi" "r24k_int_load")
-(define_bypass 2 "r24k_int_multi" "r24k_int_store" "!store_data_bypass_p")
+(define_bypass 2 "r24k_int_multi" "r24k_int_store" "!mips_store_data_bypass_p")
 (define_bypass 2 "r24k_int_multi" "r24k_int_prefetch")
 
 
@@ -330,13 +321,14 @@
 ;; r24kf2_1_fcvt_f2i->l/s base : 11 cycles
 ;; r24kf2_1_fcvt_f2i->prefetch : 11 cycles
 (define_bypass 11 "r24kf2_1_fcvt_f2i" "r24k_int_load")
-(define_bypass 11 "r24kf2_1_fcvt_f2i" "r24k_int_store" "!store_data_bypass_p")
+(define_bypass 11 "r24kf2_1_fcvt_f2i" "r24k_int_store"
+  "!mips_store_data_bypass_p")
 (define_bypass 11 "r24kf2_1_fcvt_f2i" "r24k_int_prefetch")
 
 ;; r24kf2_1_fxfer->l/s base : 5 cycles
 ;; r24kf2_1_fxfer->prefetch : 5 cycles
 (define_bypass 5 "r24kf2_1_fxfer" "r24k_int_load")
-(define_bypass 5 "r24kf2_1_fxfer" "r24k_int_store" "!store_data_bypass_p")
+(define_bypass 5 "r24kf2_1_fxfer" "r24k_int_store" "!mips_store_data_bypass_p")
 (define_bypass 5 "r24kf2_1_fxfer" "r24k_int_prefetch")
 
 ;; --------------------------------------------------------------
@@ -446,12 +438,13 @@
 ;; r24kf1_1_fcvt_f2i->l/s base : 6 cycles
 ;; r24kf1_1_fcvt_f2i->prefetch : 6 cycles
 (define_bypass 6 "r24kf1_1_fcvt_f2i" "r24k_int_load")
-(define_bypass 6 "r24kf1_1_fcvt_f2i" "r24k_int_store" "!store_data_bypass_p")
+(define_bypass 6 "r24kf1_1_fcvt_f2i" "r24k_int_store"
+  "!mips_store_data_bypass_p")
 (define_bypass 6 "r24kf1_1_fcvt_f2i" "r24k_int_prefetch")
 
 ;; r24kf1_1_fxfer->l/s base : 3 cycles
 ;; r24kf1_1_fxfer->prefetch : 3 cycles
 (define_bypass 3 "r24kf1_1_fxfer" "r24k_int_load")
-(define_bypass 3 "r24kf1_1_fxfer" "r24k_int_store" "!store_data_bypass_p")
+(define_bypass 3 "r24kf1_1_fxfer" "r24k_int_store" "!mips_store_data_bypass_p")
 (define_bypass 3 "r24kf1_1_fxfer" "r24k_int_prefetch")
 
diff --git a/gcc/config/mips/74k.md b/gcc/config/mips/74k.md
index cd0a76d..4a9cb65 100644
--- a/gcc/config/mips/74k.md
+++ b/gcc/config/mips/74k.md
@@ -118,8 +118,7 @@
 ;; stores
 (define_insn_reservation "r74k_int_store" 1
   (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
-       (and (eq_attr "type" "store")
-            (eq_attr "mode" "!unknown")))
+       (eq_attr "type" "store"))
   "r74k_agen")
 
 
@@ -145,25 +144,27 @@
 ;; load->load base:  4 cycles
 ;; load->store base: 4 cycles
 (define_bypass 4 "r74k_int_load" "r74k_int_load")
-(define_bypass 4 "r74k_int_load" "r74k_int_store" "!store_data_bypass_p")
+(define_bypass 4 "r74k_int_load" "r74k_int_store" "!mips_store_data_bypass_p")
 
 ;; logical/move/slt/signext->next use :  1 cycles (Default)
 ;; logical/move/slt/signext->load base:  2 cycles
 ;; logical/move/slt/signext->store base: 2 cycles
 (define_bypass 2 "r74k_int_logical" "r74k_int_load")
-(define_bypass 2 "r74k_int_logical" "r74k_int_store" "!store_data_bypass_p")
+(define_bypass 2 "r74k_int_logical" "r74k_int_store"
+  "!mips_store_data_bypass_p")
 
 ;; arith->next use :  2 cycles (Default)
 ;; arith->load base:  3 cycles
 ;; arith->store base: 3 cycles
 (define_bypass 3 "r74k_int_arith" "r74k_int_load")
-(define_bypass 3 "r74k_int_arith" "r74k_int_store" "!store_data_bypass_p")
+(define_bypass 3 "r74k_int_arith" "r74k_int_store" "!mips_store_data_bypass_p")
 
 ;; cmove->next use :  4 cycles (Default)
 ;; cmove->load base:  5 cycles
 ;; cmove->store base: 5 cycles
 (define_bypass 5 "r74k_int_cmove"  "r74k_int_load")
-(define_bypass 5 "r74k_int_cmove"  "r74k_int_store" "!store_data_bypass_p")
+(define_bypass 5 "r74k_int_cmove"  "r74k_int_store"
+  "!mips_store_data_bypass_p")
 
 ;; mult/madd/msub->int_mfhilo  : 4 cycles (default)
 ;; mult->madd/msub             : 1 cycles