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| author | Christophe Lyon <christophe.lyon@linaro.org> | 2017-11-06 10:43:19 +0000 |
|---|---|---|
| committer | Christophe Lyon <clyon@gcc.gnu.org> | 2017-11-06 11:43:19 +0100 |
| commit | d276dc3174209bfa5a8199a8b9fd7bec176c26b1 (patch) | |
| tree | 1e257a8eb7823b79df301abae72ce3a8b6b0f8ef /gcc | |
| parent | caa3209ec286d48a267d347cd95bfd34c17ac1e3 (diff) | |
| download | gcc-d276dc3174209bfa5a8199a8b9fd7bec176c26b1.zip gcc-d276dc3174209bfa5a8199a8b9fd7bec176c26b1.tar.gz gcc-d276dc3174209bfa5a8199a8b9fd7bec176c26b1.tar.bz2 | |
[ARM] PR 67591 ARM v8 Thumb IT blocks are deprecated part 2
2017-11-06 Christophe Lyon <christophe.lyon@linaro.org>
PR target/67591
* config/arm/arm.md (*sub_shiftsi): Add predicable_short_it
attribute.
(*cmp_ite0): Add enabled_for_depr_it attribute.
(*cmp_ite1): Likewise.
From-SVN: r254446
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/config/arm/arm.md | 3 |
2 files changed, 11 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c4a360f..b21c5fc 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2017-11-06 Christophe Lyon <christophe.lyon@linaro.org> + + PR target/67591 + * config/arm/arm.md (*sub_shiftsi): Add predicable_short_it + attribute. + (*cmp_ite0): Add enabled_for_depr_it attribute. + (*cmp_ite1): Likewise. + 2017-11-06 Segher Boessenkool <segher@kernel.crashing.org> * config/rs6000/rs6000.c (rs6000_insn_cost): Handle TYPE_MFCR and diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index ddb9d8f..7f6f0d2 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -8906,6 +8906,7 @@ "TARGET_32BIT" "sub%?\\t%0, %1, %3%S2" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "shift" "3") (set_attr "arch" "32,a") (set_attr "type" "alus_shift_imm,alus_shift_reg")]) @@ -9344,6 +9345,7 @@ }" [(set_attr "conds" "set") (set_attr "arch" "t2,t2,t2,t2,t2,any,any,any,any") + (set_attr "enabled_for_depr_it" "yes,no,no,no,no,no,no,no,no") (set_attr "type" "multiple") (set_attr_alternative "length" [(const_int 6) @@ -9427,6 +9429,7 @@ }" [(set_attr "conds" "set") (set_attr "arch" "t2,t2,t2,t2,t2,any,any,any,any") + (set_attr "enabled_for_depr_it" "yes,no,no,no,no,no,no,no,no") (set_attr_alternative "length" [(const_int 6) (const_int 8) |