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| author | Maciej W. Rozycki <macro@imgtec.com> | 2016-11-16 21:35:02 +0000 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@gcc.gnu.org> | 2016-11-16 21:35:02 +0000 |
| commit | d08c0ea31303046ce5e7da8ba8a2ff112589bc86 (patch) | |
| tree | 4974835cb04e2868ad3d0eb7b5927ced442fd606 /gcc | |
| parent | fc72d1ed3c8b11437981487755a7d6edfaf06d22 (diff) | |
| download | gcc-d08c0ea31303046ce5e7da8ba8a2ff112589bc86.zip gcc-d08c0ea31303046ce5e7da8ba8a2ff112589bc86.tar.gz gcc-d08c0ea31303046ce5e7da8ba8a2ff112589bc86.tar.bz2 | |
MIPS16/GCC: Fix DImode `casesi_internal_mips16_<mode>' assembly instructions
gcc/
* config/mips/mips.md (casesi_internal_mips16_<mode>): Add
missing <d> instruction prefixes throughout. Correct
formatting.
gcc/testsuite/
* gcc.target/mips/code-readable-4.c (dg-final): Expect `dla'
rather than `la'.
From-SVN: r242514
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/mips/mips.md | 12 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/mips/code-readable-4.c | 2 |
4 files changed, 18 insertions, 7 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 4e437f0..30161a0 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,11 @@ 2016-11-16 Maciej W. Rozycki <macro@imgtec.com> + * config/mips/mips.md (casesi_internal_mips16_<mode>): Add + missing <d> instruction prefixes throughout. Correct + formatting. + +2016-11-16 Maciej W. Rozycki <macro@imgtec.com> + * config/mips/mips.c (mips_output_jump): Output R_MICROMIPS_JALR rather than R_MIPS_JALR relocation in microMIPS code. Do not cancel short delay slots in PIC call relaxation. diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index dc071d5..0ccee9e 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -6424,14 +6424,14 @@ { case HImode: output_asm_insn ("sll\t%5, %0, 1", operands); - output_asm_insn ("la\t%4, %2", operands); + output_asm_insn ("<d>la\t%4, %2", operands); output_asm_insn ("<d>addu\t%5, %4, %5", operands); output_asm_insn ("lh\t%5, 0(%5)", operands); break; - + case SImode: output_asm_insn ("sll\t%5, %0, 2", operands); - output_asm_insn ("la\t%4, %2", operands); + output_asm_insn ("<d>la\t%4, %2", operands); output_asm_insn ("<d>addu\t%5, %4, %5", operands); output_asm_insn ("lw\t%5, 0(%5)", operands); break; @@ -6439,9 +6439,9 @@ default: gcc_unreachable (); } - - output_asm_insn ("addu\t%4, %4, %5", operands); - + + output_asm_insn ("<d>addu\t%4, %4, %5", operands); + return "j\t%4"; } [(set_attr "insn_count" "16")]) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 0677079..3707e7c 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,10 @@ 2016-11-16 Maciej W. Rozycki <macro@imgtec.com> + * gcc.target/mips/code-readable-4.c (dg-final): Expect `dla' + rather than `la'. + +2016-11-16 Maciej W. Rozycki <macro@imgtec.com> + * gcc.target/mips/call-1.c (dg-options): Add `-mno-micromips'. (dg-final): Remove microMIPS JALRS mnemonic matching. * gcc.target/mips/call-2.c (dg-options): Add `-mno-micromips'. diff --git a/gcc/testsuite/gcc.target/mips/code-readable-4.c b/gcc/testsuite/gcc.target/mips/code-readable-4.c index beb9248..1a6fdf4 100644 --- a/gcc/testsuite/gcc.target/mips/code-readable-4.c +++ b/gcc/testsuite/gcc.target/mips/code-readable-4.c @@ -41,7 +41,7 @@ bar (void) return k; } -/* { dg-final { scan-assembler "\tla\t" } } */ +/* { dg-final { scan-assembler "\tdla\t" } } */ /* { dg-final { scan-assembler "\t\\.half\t" } } */ /* { dg-final { scan-assembler-not "%hi\\(\[^)\]*L" } } */ /* { dg-final { scan-assembler-not "%lo\\(\[^)\]*L" } } */ |