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| author | David S. Miller <davem@davemloft.net> | 2011-09-26 20:21:19 +0000 |
|---|---|---|
| committer | David S. Miller <davem@gcc.gnu.org> | 2011-09-26 13:21:19 -0700 |
| commit | caa06916332c09b639863c5021aaa1c1a4b40988 (patch) | |
| tree | f1a2d8655f444bedd16919923de7767bf94e1f5a /gcc | |
| parent | ef71fdd925864fd461bd18cd52218495b457b29b (diff) | |
| download | gcc-caa06916332c09b639863c5021aaa1c1a4b40988.zip gcc-caa06916332c09b639863c5021aaa1c1a4b40988.tar.gz gcc-caa06916332c09b639863c5021aaa1c1a4b40988.tar.bz2 | |
Fix sparc %gsr write elimination and add a testcase.
gcc/
* config/sparc/sparc.c (sparc_conditional_register_usage): When VIS
is enabled, mark %gsr as global.
* config/sparc/sparc.md (UNSPEC_WRGSR): Delete.
(wrgsr_vis, *wrgsr_sp64, wrgsr_v8plus): Don't wrap in an unspec.
gcc/testsuite/
* gcc.target/sparc/wrgsr.c: New test.
From-SVN: r179214
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/sparc/sparc.c | 2 | ||||
| -rw-r--r-- | gcc/config/sparc/sparc.md | 11 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/sparc/wrgsr.c | 15 |
5 files changed, 30 insertions, 7 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 309eca5..53afbd9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2011-09-26 David S. Miller <davem@davemloft.net> + * config/sparc/sparc.c (sparc_conditional_register_usage): When VIS + is enabled, mark %gsr as global. + * config/sparc/sparc.md (UNSPEC_WRGSR): Delete. + (wrgsr_vis, *wrgsr_sp64, wrgsr_v8plus): Don't wrap in an unspec. + * config/sparc/sparc-c.c: New file implementing sparc_target_macros, which will now define __VIS and __VIS__ when -mvis is enabled. * config/sparc/t-sparc: Likewise. diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index 8193d1c..a395321 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -10426,6 +10426,8 @@ sparc_conditional_register_usage (void) for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) leaf_reg_remap [regno] = regno; } + if (TARGET_VIS) + global_regs[SPARC_GSR_REG] = 1; } /* Implement TARGET_PREFERRED_RELOAD_CLASS diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index 3f7a93b..e79e842 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -58,7 +58,7 @@ (UNSPEC_MUL8UL 46) (UNSPEC_MULDUL 47) (UNSPEC_ALIGNDATA 48) - (UNSPEC_WRGSR 49) + (UNSPEC_PDIST 50) (UNSPEC_EDGE8 51) (UNSPEC_EDGE8L 52) @@ -7953,8 +7953,7 @@ (set_attr "fptype" "double")]) (define_expand "wrgsr_vis" - [(set (reg:DI GSR_REG) (unspec:DI [(match_operand:DI 0 "arith_operand" "")] - UNSPEC_WRGSR))] + [(set (reg:DI GSR_REG) (match_operand:DI 0 "arith_operand" ""))] "TARGET_VIS" { if (! TARGET_ARCH64) @@ -7965,15 +7964,13 @@ }) (define_insn "*wrgsr_sp64" - [(set (reg:DI GSR_REG) (unspec:DI [(match_operand:DI 0 "arith_operand" "rI")] - UNSPEC_WRGSR))] + [(set (reg:DI GSR_REG) (match_operand:DI 0 "arith_operand" "rI"))] "TARGET_VIS && TARGET_ARCH64" "wr\t%%g0, %0, %%gsr" [(set_attr "type" "gsr")]) (define_insn "wrgsr_v8plus" - [(set (reg:DI GSR_REG) (unspec:DI [(match_operand:DI 0 "arith_operand" "I,r")] - UNSPEC_WRGSR)) + [(set (reg:DI GSR_REG) (match_operand:DI 0 "arith_operand" "I,r")) (clobber (match_scratch:SI 1 "=X,&h"))] "TARGET_VIS && ! TARGET_ARCH64" { diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index c973b42..c8619b8 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2011-09-26 David S. Miller <davem@davemloft.net> + + * gcc.target/sparc/wrgsr.c: New test. + 2011-09-26 Janus Weil <janus@gcc.gnu.org> PR fortran/50515 diff --git a/gcc/testsuite/gcc.target/sparc/wrgsr.c b/gcc/testsuite/gcc.target/sparc/wrgsr.c new file mode 100644 index 0000000..6cfa060 --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/wrgsr.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O -mcpu=ultrasparc -mvis" } */ + +void set_gsr (void) +{ + __builtin_vis_write_gsr (2 << 3); +} + +void set_gsr2 (long x) +{ + __builtin_vis_write_gsr (x); +} + +/* { dg-final { scan-assembler "wr\t%g0, 16, %gsr" } } */ +/* { dg-final { scan-assembler "wr\t%g0, %" } } */ |