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author | Roger Sayle <roger@nextmovesoftware.com> | 2022-07-05 18:06:13 +0100 |
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committer | Roger Sayle <roger@nextmovesoftware.com> | 2022-07-05 18:06:13 +0100 |
commit | c73e8d45ca0111f51d7187641963df97f5c9c63f (patch) | |
tree | 7d8ae0764e0b46a32a6444af40917e7e457206f4 /gcc | |
parent | 02e2e15ec4b610c0f5c73e1db424b1bbc65dd39a (diff) | |
download | gcc-c73e8d45ca0111f51d7187641963df97f5c9c63f.zip gcc-c73e8d45ca0111f51d7187641963df97f5c9c63f.tar.gz gcc-c73e8d45ca0111f51d7187641963df97f5c9c63f.tar.bz2 |
Doubleword version of and;cmp to not;test optimization on x86.
This patch extends the earlier and;cmp to not;test optimization to also
perform this transformation for TImode on TARGET_64BIT and DImode on -m32,
One motivation for this is that it's a step to fixing the current failure
of gcc.target/i386/pr65105-5.c on -m32.
A more direct benefit for x86_64 is that the following code:
int foo(__int128 x, __int128 y)
{
return (x & y) == y;
}
improves with -O2 from 15 instructions:
movq %rdi, %r8
movq %rsi, %rax
movq %rax, %rdi
movq %r8, %rsi
movq %rdx, %r8
andq %rdx, %rsi
andq %rcx, %rdi
movq %rsi, %rax
movq %rdi, %rdx
xorq %r8, %rax
xorq %rcx, %rdx
orq %rdx, %rax
sete %al
movzbl %al, %eax
ret
to the slightly better 13 instructions:
movq %rdi, %r8
movq %rsi, %rax
movq %r8, %rsi
movq %rax, %rdi
notq %rsi
notq %rdi
andq %rdx, %rsi
andq %rcx, %rdi
movq %rsi, %rax
orq %rdi, %rax
sete %al
movzbl %al, %eax
ret
2022-07-05 Roger Sayle <roger@nextmovesoftware.com>
gcc/ChangeLog
* config/i386/i386.cc (ix86_rtx_costs) <COMPARE>: Provide costs
for double word comparisons and tests (comparisons against zero).
* config/i386/i386.md (*test<mode>_not_doubleword): Split DWI
and;cmp into andn;cmp $0 as a pre-reload splitter.
(*andn<dwi>3_doubleword_bmi): Use <dwi> instead of <mode> in name.
(*<any_or><dwi>3_doubleword): Likewise.
gcc/testsuite/ChangeLog
* gcc.target/i386/testnot-3.c: New test case.
Diffstat (limited to 'gcc')
-rw-r--r-- | gcc/config/i386/i386.cc | 13 | ||||
-rw-r--r-- | gcc/config/i386/i386.md | 22 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/i386/testnot-3.c | 9 |
3 files changed, 42 insertions, 2 deletions
diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc index 0cfe996..95cb1e2 100644 --- a/gcc/config/i386/i386.cc +++ b/gcc/config/i386/i386.cc @@ -20982,6 +20982,19 @@ ix86_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno, return true; } + if (SCALAR_INT_MODE_P (GET_MODE (op0)) + && GET_MODE_SIZE (GET_MODE (op0)) > UNITS_PER_WORD) + { + if (op1 == const0_rtx) + *total = cost->add + + rtx_cost (op0, GET_MODE (op0), outer_code, opno, speed); + else + *total = 3*cost->add + + rtx_cost (op0, GET_MODE (op0), outer_code, opno, speed) + + rtx_cost (op1, GET_MODE (op0), outer_code, opno, speed); + return true; + } + /* The embedded comparison operand is completely free. */ if (!general_operand (op0, GET_MODE (op0)) && op1 == const0_rtx) *total = 0; diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index d114754..bdde577 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -9792,7 +9792,25 @@ (set (reg:CCZ FLAGS_REG) (compare:CCZ (and:SWI (match_dup 2) (match_dup 1)) (const_int 0)))] + "operands[2] = gen_reg_rtx (<MODE>mode);") + +;; Split and;cmp (as optimized by combine) into andn;cmp $0 +(define_insn_and_split "*test<mode>_not_doubleword" + [(set (reg:CCZ FLAGS_REG) + (compare:CCZ + (and:DWI + (not:DWI (match_operand:DWI 0 "nonimmediate_operand")) + (match_operand:DWI 1 "nonimmediate_operand")) + (const_int 0)))] + "ix86_pre_reload_split ()" + "#" + "&& 1" + [(parallel + [(set (match_dup 2) (and:DWI (not:DWI (match_dup 0)) (match_dup 1))) + (clobber (reg:CC FLAGS_REG))]) + (set (reg:CCZ FLAGS_REG) (compare:CCZ (match_dup 2) (const_int 0)))] { + operands[0] = force_reg (<MODE>mode, operands[0]); operands[2] = gen_reg_rtx (<MODE>mode); }) @@ -10404,7 +10422,7 @@ operands[2] = gen_int_mode (INTVAL (operands[2]), QImode); }) -(define_insn_and_split "*andn<mode>3_doubleword_bmi" +(define_insn_and_split "*andn<dwi>3_doubleword_bmi" [(set (match_operand:<DWI> 0 "register_operand" "=r") (and:<DWI> (not:<DWI> (match_operand:<DWI> 1 "register_operand" "r")) @@ -10618,7 +10636,7 @@ DONE; }) -(define_insn_and_split "*<code><mode>3_doubleword" +(define_insn_and_split "*<code><dwi>3_doubleword" [(set (match_operand:<DWI> 0 "nonimmediate_operand" "=ro,r") (any_or:<DWI> (match_operand:<DWI> 1 "nonimmediate_operand" "%0,0") diff --git a/gcc/testsuite/gcc.target/i386/testnot-3.c b/gcc/testsuite/gcc.target/i386/testnot-3.c new file mode 100644 index 0000000..7c54dbc --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/testnot-3.c @@ -0,0 +1,9 @@ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-O2" } */ + +int foo(__int128 x, __int128 y) +{ + return (x & y) == y; +} + +/* { dg-final { scan-assembler-not "xorq" } } */ |