RISC-V: Add vwmacc vx C++ api tests

gcc/testsuite/ChangeLog:

	* g++.target/riscv/rvv/base/vwmacc_vx-1.C: New test.
	* g++.target/riscv/rvv/base/vwmacc_vx-2.C: New test.
	* g++.target/riscv/rvv/base/vwmacc_vx-3.C: New test.
	* g++.target/riscv/rvv/base/vwmacc_vx_mu-1.C: New test.
	* g++.target/riscv/rvv/base/vwmacc_vx_mu-2.C: New test.
	* g++.target/riscv/rvv/base/vwmacc_vx_mu-3.C: New test.
	* g++.target/riscv/rvv/base/vwmacc_vx_tu-1.C: New test.
	* g++.target/riscv/rvv/base/vwmacc_vx_tu-2.C: New test.
	* g++.target/riscv/rvv/base/vwmacc_vx_tu-3.C: New test.
	* g++.target/riscv/rvv/base/vwmacc_vx_tum-1.C: New test.
	* g++.target/riscv/rvv/base/vwmacc_vx_tum-2.C: New test.
	* g++.target/riscv/rvv/base/vwmacc_vx_tum-3.C: New test.
	* g++.target/riscv/rvv/base/vwmacc_vx_tumu-1.C: New test.
	* g++.target/riscv/rvv/base/vwmacc_vx_tumu-2.C: New test.
	* g++.target/riscv/rvv/base/vwmacc_vx_tumu-3.C: New test.
	* g++.target/riscv/rvv/base/vwmaccsu_vx-1.C: New test.
	* g++.target/riscv/rvv/base/vwmaccsu_vx-2.C: New test.
	* g++.target/riscv/rvv/base/vwmaccsu_vx-3.C: New test.
	* g++.target/riscv/rvv/base/vwmaccsu_vx_mu-1.C: New test.
	* g++.target/riscv/rvv/base/vwmaccsu_vx_mu-2.C: New test.
	* g++.target/riscv/rvv/base/vwmaccsu_vx_mu-3.C: New test.
	* g++.target/riscv/rvv/base/vwmaccsu_vx_tu-1.C: New test.
	* g++.target/riscv/rvv/base/vwmaccsu_vx_tu-2.C: New test.
	* g++.target/riscv/rvv/base/vwmaccsu_vx_tu-3.C: New test.
	* g++.target/riscv/rvv/base/vwmaccsu_vx_tum-1.C: New test.
	* g++.target/riscv/rvv/base/vwmaccsu_vx_tum-2.C: New test.
	* g++.target/riscv/rvv/base/vwmaccsu_vx_tum-3.C: New test.
	* g++.target/riscv/rvv/base/vwmaccsu_vx_tumu-1.C: New test.
	* g++.target/riscv/rvv/base/vwmaccsu_vx_tumu-2.C: New test.
	* g++.target/riscv/rvv/base/vwmaccsu_vx_tumu-3.C: New test.
	* g++.target/riscv/rvv/base/vwmaccu_vx-1.C: New test.
	* g++.target/riscv/rvv/base/vwmaccu_vx-2.C: New test.
	* g++.target/riscv/rvv/base/vwmaccu_vx-3.C: New test.
	* g++.target/riscv/rvv/base/vwmaccu_vx_mu-1.C: New test.
	* g++.target/riscv/rvv/base/vwmaccu_vx_mu-2.C: New test.
	* g++.target/riscv/rvv/base/vwmaccu_vx_mu-3.C: New test.
	* g++.target/riscv/rvv/base/vwmaccu_vx_tu-1.C: New test.
	* g++.target/riscv/rvv/base/vwmaccu_vx_tu-2.C: New test.
	* g++.target/riscv/rvv/base/vwmaccu_vx_tu-3.C: New test.
	* g++.target/riscv/rvv/base/vwmaccu_vx_tum-1.C: New test.
	* g++.target/riscv/rvv/base/vwmaccu_vx_tum-2.C: New test.
	* g++.target/riscv/rvv/base/vwmaccu_vx_tum-3.C: New test.
	* g++.target/riscv/rvv/base/vwmaccu_vx_tumu-1.C: New test.
	* g++.target/riscv/rvv/base/vwmaccu_vx_tumu-2.C: New test.
	* g++.target/riscv/rvv/base/vwmaccu_vx_tumu-3.C: New test.
	* g++.target/riscv/rvv/base/vwmaccus_vx-1.C: New test.
	* g++.target/riscv/rvv/base/vwmaccus_vx-2.C: New test.
	* g++.target/riscv/rvv/base/vwmaccus_vx-3.C: New test.
	* g++.target/riscv/rvv/base/vwmaccus_vx_mu-1.C: New test.
	* g++.target/riscv/rvv/base/vwmaccus_vx_mu-2.C: New test.
	* g++.target/riscv/rvv/base/vwmaccus_vx_mu-3.C: New test.
	* g++.target/riscv/rvv/base/vwmaccus_vx_tu-1.C: New test.
	* g++.target/riscv/rvv/base/vwmaccus_vx_tu-2.C: New test.
	* g++.target/riscv/rvv/base/vwmaccus_vx_tu-3.C: New test.
	* g++.target/riscv/rvv/base/vwmaccus_vx_tum-1.C: New test.
	* g++.target/riscv/rvv/base/vwmaccus_vx_tum-2.C: New test.
	* g++.target/riscv/rvv/base/vwmaccus_vx_tum-3.C: New test.
	* g++.target/riscv/rvv/base/vwmaccus_vx_tumu-1.C: New test.
	* g++.target/riscv/rvv/base/vwmaccus_vx_tumu-2.C: New test.
	* g++.target/riscv/rvv/base/vwmaccus_vx_tumu-3.C: New test.

60 files changed, 7920 insertions, 0 deletions

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx-1.C
new file mode 100644
index 0000000..8c96d81
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx-1.C
@@ -0,0 +1,216 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc(vint16mf4_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,rs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmacc(vint16mf2_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,rs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmacc(vint16m1_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,rs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmacc(vint16m2_t vd,int8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,rs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmacc(vint16m4_t vd,int8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,rs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmacc(vint16m8_t vd,int8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,rs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmacc(vint32mf2_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,rs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmacc(vint32m1_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,rs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmacc(vint32m2_t vd,int16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,rs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmacc(vint32m4_t vd,int16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,rs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmacc(vint32m8_t vd,int16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,rs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmacc(vint64m1_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,rs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmacc(vint64m2_t vd,int32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,rs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmacc(vint64m4_t vd,int32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,rs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmacc(vint64m8_t vd,int32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,rs1,vs2,vl);
+}
+
+
+vint16mf4_t test___riscv_vwmacc(vbool64_t mask,vint16mf4_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmacc(vbool32_t mask,vint16mf2_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmacc(vbool16_t mask,vint16m1_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmacc(vbool8_t mask,vint16m2_t vd,int8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmacc(vbool4_t mask,vint16m4_t vd,int8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmacc(vbool2_t mask,vint16m8_t vd,int8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmacc(vbool64_t mask,vint32mf2_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmacc(vbool32_t mask,vint32m1_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmacc(vbool16_t mask,vint32m2_t vd,int16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmacc(vbool8_t mask,vint32m4_t vd,int16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmacc(vbool4_t mask,vint32m8_t vd,int16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmacc(vbool64_t mask,vint64m1_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmacc(vbool32_t mask,vint64m2_t vd,int32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmacc(vbool16_t mask,vint64m4_t vd,int32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmacc(vbool8_t mask,vint64m8_t vd,int32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,rs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx-2.C
new file mode 100644
index 0000000..6ca77e5
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx-2.C
@@ -0,0 +1,216 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc(vint16mf4_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,rs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmacc(vint16mf2_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,rs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmacc(vint16m1_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,rs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmacc(vint16m2_t vd,int8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,rs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmacc(vint16m4_t vd,int8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,rs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmacc(vint16m8_t vd,int8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,rs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmacc(vint32mf2_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,rs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmacc(vint32m1_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,rs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmacc(vint32m2_t vd,int16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,rs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmacc(vint32m4_t vd,int16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,rs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmacc(vint32m8_t vd,int16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,rs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmacc(vint64m1_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,rs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmacc(vint64m2_t vd,int32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,rs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmacc(vint64m4_t vd,int32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,rs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmacc(vint64m8_t vd,int32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,rs1,vs2,31);
+}
+
+
+vint16mf4_t test___riscv_vwmacc(vbool64_t mask,vint16mf4_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,rs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmacc(vbool32_t mask,vint16mf2_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmacc(vbool16_t mask,vint16m1_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmacc(vbool8_t mask,vint16m2_t vd,int8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmacc(vbool4_t mask,vint16m4_t vd,int8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmacc(vbool2_t mask,vint16m8_t vd,int8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,rs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmacc(vbool64_t mask,vint32mf2_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmacc(vbool32_t mask,vint32m1_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmacc(vbool16_t mask,vint32m2_t vd,int16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmacc(vbool8_t mask,vint32m4_t vd,int16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmacc(vbool4_t mask,vint32m8_t vd,int16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmacc(vbool64_t mask,vint64m1_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmacc(vbool32_t mask,vint64m2_t vd,int32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmacc(vbool16_t mask,vint64m4_t vd,int32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmacc(vbool8_t mask,vint64m8_t vd,int32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,rs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx-3.C
new file mode 100644
index 0000000..31929a5
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx-3.C
@@ -0,0 +1,216 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc(vint16mf4_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,rs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmacc(vint16mf2_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,rs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmacc(vint16m1_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,rs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmacc(vint16m2_t vd,int8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,rs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmacc(vint16m4_t vd,int8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,rs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmacc(vint16m8_t vd,int8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,rs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmacc(vint32mf2_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,rs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmacc(vint32m1_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,rs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmacc(vint32m2_t vd,int16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,rs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmacc(vint32m4_t vd,int16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,rs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmacc(vint32m8_t vd,int16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,rs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmacc(vint64m1_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,rs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmacc(vint64m2_t vd,int32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,rs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmacc(vint64m4_t vd,int32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,rs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmacc(vint64m8_t vd,int32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,rs1,vs2,32);
+}
+
+
+vint16mf4_t test___riscv_vwmacc(vbool64_t mask,vint16mf4_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,rs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmacc(vbool32_t mask,vint16mf2_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmacc(vbool16_t mask,vint16m1_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmacc(vbool8_t mask,vint16m2_t vd,int8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmacc(vbool4_t mask,vint16m4_t vd,int8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmacc(vbool2_t mask,vint16m8_t vd,int8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,rs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmacc(vbool64_t mask,vint32mf2_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmacc(vbool32_t mask,vint32m1_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmacc(vbool16_t mask,vint32m2_t vd,int16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmacc(vbool8_t mask,vint32m4_t vd,int16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmacc(vbool4_t mask,vint32m8_t vd,int16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmacc(vbool64_t mask,vint64m1_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmacc(vbool32_t mask,vint64m2_t vd,int32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmacc(vbool16_t mask,vint64m4_t vd,int32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmacc(vbool8_t mask,vint64m8_t vd,int32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,rs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx_mu-1.C
new file mode 100644
index 0000000..63b38f8
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx_mu-1.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_mu(vbool64_t mask,vint16mf4_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_mu(vbool32_t mask,vint16mf2_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmacc_mu(vbool16_t mask,vint16m1_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmacc_mu(vbool8_t mask,vint16m2_t vd,int8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmacc_mu(vbool4_t mask,vint16m4_t vd,int8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmacc_mu(vbool2_t mask,vint16m8_t vd,int8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_mu(vbool64_t mask,vint32mf2_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmacc_mu(vbool32_t mask,vint32m1_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmacc_mu(vbool16_t mask,vint32m2_t vd,int16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmacc_mu(vbool8_t mask,vint32m4_t vd,int16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmacc_mu(vbool4_t mask,vint32m8_t vd,int16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmacc_mu(vbool64_t mask,vint64m1_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmacc_mu(vbool32_t mask,vint64m2_t vd,int32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmacc_mu(vbool16_t mask,vint64m4_t vd,int32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmacc_mu(vbool8_t mask,vint64m8_t vd,int32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx_mu-2.C
new file mode 100644
index 0000000..4d10cfb
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx_mu-2.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_mu(vbool64_t mask,vint16mf4_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_mu(vbool32_t mask,vint16mf2_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmacc_mu(vbool16_t mask,vint16m1_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmacc_mu(vbool8_t mask,vint16m2_t vd,int8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmacc_mu(vbool4_t mask,vint16m4_t vd,int8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmacc_mu(vbool2_t mask,vint16m8_t vd,int8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_mu(vbool64_t mask,vint32mf2_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmacc_mu(vbool32_t mask,vint32m1_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmacc_mu(vbool16_t mask,vint32m2_t vd,int16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmacc_mu(vbool8_t mask,vint32m4_t vd,int16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmacc_mu(vbool4_t mask,vint32m8_t vd,int16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmacc_mu(vbool64_t mask,vint64m1_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmacc_mu(vbool32_t mask,vint64m2_t vd,int32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmacc_mu(vbool16_t mask,vint64m4_t vd,int32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmacc_mu(vbool8_t mask,vint64m8_t vd,int32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,rs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx_mu-3.C
new file mode 100644
index 0000000..9b62375
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx_mu-3.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_mu(vbool64_t mask,vint16mf4_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_mu(vbool32_t mask,vint16mf2_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmacc_mu(vbool16_t mask,vint16m1_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmacc_mu(vbool8_t mask,vint16m2_t vd,int8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmacc_mu(vbool4_t mask,vint16m4_t vd,int8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmacc_mu(vbool2_t mask,vint16m8_t vd,int8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_mu(vbool64_t mask,vint32mf2_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmacc_mu(vbool32_t mask,vint32m1_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmacc_mu(vbool16_t mask,vint32m2_t vd,int16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmacc_mu(vbool8_t mask,vint32m4_t vd,int16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmacc_mu(vbool4_t mask,vint32m8_t vd,int16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmacc_mu(vbool64_t mask,vint64m1_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmacc_mu(vbool32_t mask,vint64m2_t vd,int32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmacc_mu(vbool16_t mask,vint64m4_t vd,int32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmacc_mu(vbool8_t mask,vint64m8_t vd,int32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,rs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx_tu-1.C
new file mode 100644
index 0000000..613840a
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx_tu-1.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_tu(vint16mf4_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,rs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_tu(vint16mf2_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,rs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmacc_tu(vint16m1_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,rs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmacc_tu(vint16m2_t vd,int8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,rs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmacc_tu(vint16m4_t vd,int8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,rs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmacc_tu(vint16m8_t vd,int8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,rs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_tu(vint32mf2_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,rs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmacc_tu(vint32m1_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,rs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmacc_tu(vint32m2_t vd,int16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,rs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmacc_tu(vint32m4_t vd,int16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,rs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmacc_tu(vint32m8_t vd,int16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,rs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmacc_tu(vint64m1_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,rs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmacc_tu(vint64m2_t vd,int32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,rs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmacc_tu(vint64m4_t vd,int32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,rs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmacc_tu(vint64m8_t vd,int32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,rs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx_tu-2.C
new file mode 100644
index 0000000..919b0af
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx_tu-2.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_tu(vint16mf4_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,rs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_tu(vint16mf2_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,rs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmacc_tu(vint16m1_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,rs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmacc_tu(vint16m2_t vd,int8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,rs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmacc_tu(vint16m4_t vd,int8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,rs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmacc_tu(vint16m8_t vd,int8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,rs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_tu(vint32mf2_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,rs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmacc_tu(vint32m1_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,rs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmacc_tu(vint32m2_t vd,int16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,rs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmacc_tu(vint32m4_t vd,int16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,rs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmacc_tu(vint32m8_t vd,int16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,rs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmacc_tu(vint64m1_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,rs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmacc_tu(vint64m2_t vd,int32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,rs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmacc_tu(vint64m4_t vd,int32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,rs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmacc_tu(vint64m8_t vd,int32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,rs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx_tu-3.C
new file mode 100644
index 0000000..19bd806
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx_tu-3.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_tu(vint16mf4_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,rs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_tu(vint16mf2_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,rs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmacc_tu(vint16m1_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,rs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmacc_tu(vint16m2_t vd,int8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,rs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmacc_tu(vint16m4_t vd,int8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,rs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmacc_tu(vint16m8_t vd,int8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,rs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_tu(vint32mf2_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,rs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmacc_tu(vint32m1_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,rs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmacc_tu(vint32m2_t vd,int16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,rs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmacc_tu(vint32m4_t vd,int16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,rs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmacc_tu(vint32m8_t vd,int16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,rs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmacc_tu(vint64m1_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,rs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmacc_tu(vint64m2_t vd,int32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,rs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmacc_tu(vint64m4_t vd,int32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,rs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmacc_tu(vint64m8_t vd,int32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,rs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx_tum-1.C
new file mode 100644
index 0000000..09268e0
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx_tum-1.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_tum(vbool64_t mask,vint16mf4_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_tum(vbool32_t mask,vint16mf2_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmacc_tum(vbool16_t mask,vint16m1_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmacc_tum(vbool8_t mask,vint16m2_t vd,int8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmacc_tum(vbool4_t mask,vint16m4_t vd,int8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmacc_tum(vbool2_t mask,vint16m8_t vd,int8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_tum(vbool64_t mask,vint32mf2_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmacc_tum(vbool32_t mask,vint32m1_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmacc_tum(vbool16_t mask,vint32m2_t vd,int16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmacc_tum(vbool8_t mask,vint32m4_t vd,int16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmacc_tum(vbool4_t mask,vint32m8_t vd,int16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmacc_tum(vbool64_t mask,vint64m1_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmacc_tum(vbool32_t mask,vint64m2_t vd,int32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmacc_tum(vbool16_t mask,vint64m4_t vd,int32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmacc_tum(vbool8_t mask,vint64m8_t vd,int32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx_tum-2.C
new file mode 100644
index 0000000..4de53bf5
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx_tum-2.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_tum(vbool64_t mask,vint16mf4_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_tum(vbool32_t mask,vint16mf2_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmacc_tum(vbool16_t mask,vint16m1_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmacc_tum(vbool8_t mask,vint16m2_t vd,int8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmacc_tum(vbool4_t mask,vint16m4_t vd,int8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmacc_tum(vbool2_t mask,vint16m8_t vd,int8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_tum(vbool64_t mask,vint32mf2_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmacc_tum(vbool32_t mask,vint32m1_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmacc_tum(vbool16_t mask,vint32m2_t vd,int16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmacc_tum(vbool8_t mask,vint32m4_t vd,int16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmacc_tum(vbool4_t mask,vint32m8_t vd,int16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmacc_tum(vbool64_t mask,vint64m1_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmacc_tum(vbool32_t mask,vint64m2_t vd,int32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmacc_tum(vbool16_t mask,vint64m4_t vd,int32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmacc_tum(vbool8_t mask,vint64m8_t vd,int32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,rs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx_tum-3.C
new file mode 100644
index 0000000..27d9ce7
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx_tum-3.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_tum(vbool64_t mask,vint16mf4_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_tum(vbool32_t mask,vint16mf2_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmacc_tum(vbool16_t mask,vint16m1_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmacc_tum(vbool8_t mask,vint16m2_t vd,int8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmacc_tum(vbool4_t mask,vint16m4_t vd,int8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmacc_tum(vbool2_t mask,vint16m8_t vd,int8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_tum(vbool64_t mask,vint32mf2_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmacc_tum(vbool32_t mask,vint32m1_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmacc_tum(vbool16_t mask,vint32m2_t vd,int16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmacc_tum(vbool8_t mask,vint32m4_t vd,int16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmacc_tum(vbool4_t mask,vint32m8_t vd,int16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmacc_tum(vbool64_t mask,vint64m1_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmacc_tum(vbool32_t mask,vint64m2_t vd,int32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmacc_tum(vbool16_t mask,vint64m4_t vd,int32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmacc_tum(vbool8_t mask,vint64m8_t vd,int32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,rs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx_tumu-1.C
new file mode 100644
index 0000000..a15c82a
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx_tumu-1.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_tumu(vbool64_t mask,vint16mf4_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_tumu(vbool32_t mask,vint16mf2_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmacc_tumu(vbool16_t mask,vint16m1_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmacc_tumu(vbool8_t mask,vint16m2_t vd,int8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmacc_tumu(vbool4_t mask,vint16m4_t vd,int8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmacc_tumu(vbool2_t mask,vint16m8_t vd,int8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_tumu(vbool64_t mask,vint32mf2_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmacc_tumu(vbool32_t mask,vint32m1_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmacc_tumu(vbool16_t mask,vint32m2_t vd,int16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmacc_tumu(vbool8_t mask,vint32m4_t vd,int16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmacc_tumu(vbool4_t mask,vint32m8_t vd,int16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmacc_tumu(vbool64_t mask,vint64m1_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmacc_tumu(vbool32_t mask,vint64m2_t vd,int32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmacc_tumu(vbool16_t mask,vint64m4_t vd,int32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmacc_tumu(vbool8_t mask,vint64m8_t vd,int32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx_tumu-2.C
new file mode 100644
index 0000000..6970d61
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx_tumu-2.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_tumu(vbool64_t mask,vint16mf4_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_tumu(vbool32_t mask,vint16mf2_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmacc_tumu(vbool16_t mask,vint16m1_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmacc_tumu(vbool8_t mask,vint16m2_t vd,int8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmacc_tumu(vbool4_t mask,vint16m4_t vd,int8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmacc_tumu(vbool2_t mask,vint16m8_t vd,int8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_tumu(vbool64_t mask,vint32mf2_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmacc_tumu(vbool32_t mask,vint32m1_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmacc_tumu(vbool16_t mask,vint32m2_t vd,int16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmacc_tumu(vbool8_t mask,vint32m4_t vd,int16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmacc_tumu(vbool4_t mask,vint32m8_t vd,int16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmacc_tumu(vbool64_t mask,vint64m1_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmacc_tumu(vbool32_t mask,vint64m2_t vd,int32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmacc_tumu(vbool16_t mask,vint64m4_t vd,int32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmacc_tumu(vbool8_t mask,vint64m8_t vd,int32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx_tumu-3.C
new file mode 100644
index 0000000..20ed158
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx_tumu-3.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_tumu(vbool64_t mask,vint16mf4_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_tumu(vbool32_t mask,vint16mf2_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmacc_tumu(vbool16_t mask,vint16m1_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmacc_tumu(vbool8_t mask,vint16m2_t vd,int8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmacc_tumu(vbool4_t mask,vint16m4_t vd,int8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmacc_tumu(vbool2_t mask,vint16m8_t vd,int8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_tumu(vbool64_t mask,vint32mf2_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmacc_tumu(vbool32_t mask,vint32m1_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmacc_tumu(vbool16_t mask,vint32m2_t vd,int16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmacc_tumu(vbool8_t mask,vint32m4_t vd,int16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmacc_tumu(vbool4_t mask,vint32m8_t vd,int16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmacc_tumu(vbool64_t mask,vint64m1_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmacc_tumu(vbool32_t mask,vint64m2_t vd,int32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmacc_tumu(vbool16_t mask,vint64m4_t vd,int32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmacc_tumu(vbool8_t mask,vint64m8_t vd,int32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmacc\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx-1.C
new file mode 100644
index 0000000..1028a72
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx-1.C
@@ -0,0 +1,216 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu(vint16mf4_t vd,int8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,rs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu(vint16mf2_t vd,int8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,rs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu(vint16m1_t vd,int8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,rs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu(vint16m2_t vd,int8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,rs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu(vint16m4_t vd,int8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,rs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu(vint16m8_t vd,int8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,rs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu(vint32mf2_t vd,int16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,rs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu(vint32m1_t vd,int16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,rs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu(vint32m2_t vd,int16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,rs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu(vint32m4_t vd,int16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,rs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu(vint32m8_t vd,int16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,rs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu(vint64m1_t vd,int32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,rs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu(vint64m2_t vd,int32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,rs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu(vint64m4_t vd,int32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,rs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu(vint64m8_t vd,int32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,rs1,vs2,vl);
+}
+
+
+vint16mf4_t test___riscv_vwmaccsu(vbool64_t mask,vint16mf4_t vd,int8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu(vbool32_t mask,vint16mf2_t vd,int8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu(vbool16_t mask,vint16m1_t vd,int8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu(vbool8_t mask,vint16m2_t vd,int8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu(vbool4_t mask,vint16m4_t vd,int8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu(vbool2_t mask,vint16m8_t vd,int8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu(vbool64_t mask,vint32mf2_t vd,int16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu(vbool32_t mask,vint32m1_t vd,int16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu(vbool16_t mask,vint32m2_t vd,int16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu(vbool8_t mask,vint32m4_t vd,int16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu(vbool4_t mask,vint32m8_t vd,int16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu(vbool64_t mask,vint64m1_t vd,int32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu(vbool32_t mask,vint64m2_t vd,int32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu(vbool16_t mask,vint64m4_t vd,int32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu(vbool8_t mask,vint64m8_t vd,int32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,rs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx-2.C
new file mode 100644
index 0000000..f0d4bac
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx-2.C
@@ -0,0 +1,216 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu(vint16mf4_t vd,int8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,rs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu(vint16mf2_t vd,int8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,rs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu(vint16m1_t vd,int8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,rs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu(vint16m2_t vd,int8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,rs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu(vint16m4_t vd,int8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,rs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu(vint16m8_t vd,int8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,rs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu(vint32mf2_t vd,int16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,rs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu(vint32m1_t vd,int16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,rs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu(vint32m2_t vd,int16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,rs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu(vint32m4_t vd,int16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,rs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu(vint32m8_t vd,int16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,rs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu(vint64m1_t vd,int32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,rs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu(vint64m2_t vd,int32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,rs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu(vint64m4_t vd,int32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,rs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu(vint64m8_t vd,int32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,rs1,vs2,31);
+}
+
+
+vint16mf4_t test___riscv_vwmaccsu(vbool64_t mask,vint16mf4_t vd,int8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,rs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu(vbool32_t mask,vint16mf2_t vd,int8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu(vbool16_t mask,vint16m1_t vd,int8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu(vbool8_t mask,vint16m2_t vd,int8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu(vbool4_t mask,vint16m4_t vd,int8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu(vbool2_t mask,vint16m8_t vd,int8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,rs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu(vbool64_t mask,vint32mf2_t vd,int16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu(vbool32_t mask,vint32m1_t vd,int16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu(vbool16_t mask,vint32m2_t vd,int16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu(vbool8_t mask,vint32m4_t vd,int16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu(vbool4_t mask,vint32m8_t vd,int16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu(vbool64_t mask,vint64m1_t vd,int32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu(vbool32_t mask,vint64m2_t vd,int32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu(vbool16_t mask,vint64m4_t vd,int32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu(vbool8_t mask,vint64m8_t vd,int32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,rs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx-3.C
new file mode 100644
index 0000000..e5a64b1
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx-3.C
@@ -0,0 +1,216 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu(vint16mf4_t vd,int8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,rs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu(vint16mf2_t vd,int8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,rs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu(vint16m1_t vd,int8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,rs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu(vint16m2_t vd,int8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,rs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu(vint16m4_t vd,int8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,rs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu(vint16m8_t vd,int8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,rs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu(vint32mf2_t vd,int16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,rs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu(vint32m1_t vd,int16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,rs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu(vint32m2_t vd,int16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,rs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu(vint32m4_t vd,int16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,rs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu(vint32m8_t vd,int16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,rs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu(vint64m1_t vd,int32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,rs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu(vint64m2_t vd,int32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,rs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu(vint64m4_t vd,int32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,rs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu(vint64m8_t vd,int32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,rs1,vs2,32);
+}
+
+
+vint16mf4_t test___riscv_vwmaccsu(vbool64_t mask,vint16mf4_t vd,int8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,rs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu(vbool32_t mask,vint16mf2_t vd,int8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu(vbool16_t mask,vint16m1_t vd,int8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu(vbool8_t mask,vint16m2_t vd,int8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu(vbool4_t mask,vint16m4_t vd,int8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu(vbool2_t mask,vint16m8_t vd,int8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,rs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu(vbool64_t mask,vint32mf2_t vd,int16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu(vbool32_t mask,vint32m1_t vd,int16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu(vbool16_t mask,vint32m2_t vd,int16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu(vbool8_t mask,vint32m4_t vd,int16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu(vbool4_t mask,vint32m8_t vd,int16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu(vbool64_t mask,vint64m1_t vd,int32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu(vbool32_t mask,vint64m2_t vd,int32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu(vbool16_t mask,vint64m4_t vd,int32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu(vbool8_t mask,vint64m8_t vd,int32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,rs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx_mu-1.C
new file mode 100644
index 0000000..728a8ff
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx_mu-1.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_mu(vbool64_t mask,vint16mf4_t vd,int8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_mu(vbool32_t mask,vint16mf2_t vd,int8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_mu(vbool16_t mask,vint16m1_t vd,int8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_mu(vbool8_t mask,vint16m2_t vd,int8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_mu(vbool4_t mask,vint16m4_t vd,int8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_mu(vbool2_t mask,vint16m8_t vd,int8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_mu(vbool64_t mask,vint32mf2_t vd,int16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_mu(vbool32_t mask,vint32m1_t vd,int16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_mu(vbool16_t mask,vint32m2_t vd,int16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_mu(vbool8_t mask,vint32m4_t vd,int16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_mu(vbool4_t mask,vint32m8_t vd,int16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_mu(vbool64_t mask,vint64m1_t vd,int32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_mu(vbool32_t mask,vint64m2_t vd,int32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_mu(vbool16_t mask,vint64m4_t vd,int32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_mu(vbool8_t mask,vint64m8_t vd,int32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx_mu-2.C
new file mode 100644
index 0000000..9f07454
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx_mu-2.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_mu(vbool64_t mask,vint16mf4_t vd,int8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_mu(vbool32_t mask,vint16mf2_t vd,int8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_mu(vbool16_t mask,vint16m1_t vd,int8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_mu(vbool8_t mask,vint16m2_t vd,int8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_mu(vbool4_t mask,vint16m4_t vd,int8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_mu(vbool2_t mask,vint16m8_t vd,int8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_mu(vbool64_t mask,vint32mf2_t vd,int16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_mu(vbool32_t mask,vint32m1_t vd,int16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_mu(vbool16_t mask,vint32m2_t vd,int16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_mu(vbool8_t mask,vint32m4_t vd,int16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_mu(vbool4_t mask,vint32m8_t vd,int16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_mu(vbool64_t mask,vint64m1_t vd,int32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_mu(vbool32_t mask,vint64m2_t vd,int32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_mu(vbool16_t mask,vint64m4_t vd,int32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_mu(vbool8_t mask,vint64m8_t vd,int32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,rs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx_mu-3.C
new file mode 100644
index 0000000..51c777e
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx_mu-3.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_mu(vbool64_t mask,vint16mf4_t vd,int8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_mu(vbool32_t mask,vint16mf2_t vd,int8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_mu(vbool16_t mask,vint16m1_t vd,int8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_mu(vbool8_t mask,vint16m2_t vd,int8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_mu(vbool4_t mask,vint16m4_t vd,int8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_mu(vbool2_t mask,vint16m8_t vd,int8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_mu(vbool64_t mask,vint32mf2_t vd,int16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_mu(vbool32_t mask,vint32m1_t vd,int16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_mu(vbool16_t mask,vint32m2_t vd,int16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_mu(vbool8_t mask,vint32m4_t vd,int16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_mu(vbool4_t mask,vint32m8_t vd,int16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_mu(vbool64_t mask,vint64m1_t vd,int32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_mu(vbool32_t mask,vint64m2_t vd,int32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_mu(vbool16_t mask,vint64m4_t vd,int32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_mu(vbool8_t mask,vint64m8_t vd,int32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,rs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx_tu-1.C
new file mode 100644
index 0000000..d77c610
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx_tu-1.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_tu(vint16mf4_t vd,int8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,rs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_tu(vint16mf2_t vd,int8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,rs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_tu(vint16m1_t vd,int8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,rs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_tu(vint16m2_t vd,int8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,rs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_tu(vint16m4_t vd,int8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,rs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_tu(vint16m8_t vd,int8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,rs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_tu(vint32mf2_t vd,int16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,rs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_tu(vint32m1_t vd,int16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,rs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_tu(vint32m2_t vd,int16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,rs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_tu(vint32m4_t vd,int16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,rs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_tu(vint32m8_t vd,int16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,rs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_tu(vint64m1_t vd,int32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,rs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_tu(vint64m2_t vd,int32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,rs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_tu(vint64m4_t vd,int32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,rs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_tu(vint64m8_t vd,int32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,rs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx_tu-2.C
new file mode 100644
index 0000000..d51692e
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx_tu-2.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_tu(vint16mf4_t vd,int8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,rs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_tu(vint16mf2_t vd,int8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,rs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_tu(vint16m1_t vd,int8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,rs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_tu(vint16m2_t vd,int8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,rs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_tu(vint16m4_t vd,int8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,rs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_tu(vint16m8_t vd,int8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,rs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_tu(vint32mf2_t vd,int16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,rs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_tu(vint32m1_t vd,int16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,rs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_tu(vint32m2_t vd,int16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,rs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_tu(vint32m4_t vd,int16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,rs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_tu(vint32m8_t vd,int16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,rs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_tu(vint64m1_t vd,int32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,rs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_tu(vint64m2_t vd,int32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,rs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_tu(vint64m4_t vd,int32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,rs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_tu(vint64m8_t vd,int32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,rs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx_tu-3.C
new file mode 100644
index 0000000..b31e241
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx_tu-3.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_tu(vint16mf4_t vd,int8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,rs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_tu(vint16mf2_t vd,int8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,rs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_tu(vint16m1_t vd,int8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,rs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_tu(vint16m2_t vd,int8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,rs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_tu(vint16m4_t vd,int8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,rs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_tu(vint16m8_t vd,int8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,rs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_tu(vint32mf2_t vd,int16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,rs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_tu(vint32m1_t vd,int16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,rs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_tu(vint32m2_t vd,int16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,rs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_tu(vint32m4_t vd,int16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,rs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_tu(vint32m8_t vd,int16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,rs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_tu(vint64m1_t vd,int32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,rs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_tu(vint64m2_t vd,int32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,rs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_tu(vint64m4_t vd,int32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,rs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_tu(vint64m8_t vd,int32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,rs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx_tum-1.C
new file mode 100644
index 0000000..913f0ec
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx_tum-1.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_tum(vbool64_t mask,vint16mf4_t vd,int8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_tum(vbool32_t mask,vint16mf2_t vd,int8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_tum(vbool16_t mask,vint16m1_t vd,int8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_tum(vbool8_t mask,vint16m2_t vd,int8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_tum(vbool4_t mask,vint16m4_t vd,int8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_tum(vbool2_t mask,vint16m8_t vd,int8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_tum(vbool64_t mask,vint32mf2_t vd,int16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_tum(vbool32_t mask,vint32m1_t vd,int16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_tum(vbool16_t mask,vint32m2_t vd,int16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_tum(vbool8_t mask,vint32m4_t vd,int16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_tum(vbool4_t mask,vint32m8_t vd,int16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_tum(vbool64_t mask,vint64m1_t vd,int32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_tum(vbool32_t mask,vint64m2_t vd,int32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_tum(vbool16_t mask,vint64m4_t vd,int32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_tum(vbool8_t mask,vint64m8_t vd,int32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx_tum-2.C
new file mode 100644
index 0000000..fe917e2
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx_tum-2.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_tum(vbool64_t mask,vint16mf4_t vd,int8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_tum(vbool32_t mask,vint16mf2_t vd,int8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_tum(vbool16_t mask,vint16m1_t vd,int8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_tum(vbool8_t mask,vint16m2_t vd,int8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_tum(vbool4_t mask,vint16m4_t vd,int8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_tum(vbool2_t mask,vint16m8_t vd,int8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_tum(vbool64_t mask,vint32mf2_t vd,int16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_tum(vbool32_t mask,vint32m1_t vd,int16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_tum(vbool16_t mask,vint32m2_t vd,int16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_tum(vbool8_t mask,vint32m4_t vd,int16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_tum(vbool4_t mask,vint32m8_t vd,int16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_tum(vbool64_t mask,vint64m1_t vd,int32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_tum(vbool32_t mask,vint64m2_t vd,int32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_tum(vbool16_t mask,vint64m4_t vd,int32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_tum(vbool8_t mask,vint64m8_t vd,int32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,rs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx_tum-3.C
new file mode 100644
index 0000000..4d6c43f
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx_tum-3.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_tum(vbool64_t mask,vint16mf4_t vd,int8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_tum(vbool32_t mask,vint16mf2_t vd,int8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_tum(vbool16_t mask,vint16m1_t vd,int8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_tum(vbool8_t mask,vint16m2_t vd,int8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_tum(vbool4_t mask,vint16m4_t vd,int8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_tum(vbool2_t mask,vint16m8_t vd,int8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_tum(vbool64_t mask,vint32mf2_t vd,int16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_tum(vbool32_t mask,vint32m1_t vd,int16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_tum(vbool16_t mask,vint32m2_t vd,int16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_tum(vbool8_t mask,vint32m4_t vd,int16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_tum(vbool4_t mask,vint32m8_t vd,int16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_tum(vbool64_t mask,vint64m1_t vd,int32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_tum(vbool32_t mask,vint64m2_t vd,int32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_tum(vbool16_t mask,vint64m4_t vd,int32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_tum(vbool8_t mask,vint64m8_t vd,int32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,rs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx_tumu-1.C
new file mode 100644
index 0000000..48dc657
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx_tumu-1.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_tumu(vbool64_t mask,vint16mf4_t vd,int8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_tumu(vbool32_t mask,vint16mf2_t vd,int8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_tumu(vbool16_t mask,vint16m1_t vd,int8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_tumu(vbool8_t mask,vint16m2_t vd,int8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_tumu(vbool4_t mask,vint16m4_t vd,int8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_tumu(vbool2_t mask,vint16m8_t vd,int8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_tumu(vbool64_t mask,vint32mf2_t vd,int16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_tumu(vbool32_t mask,vint32m1_t vd,int16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_tumu(vbool16_t mask,vint32m2_t vd,int16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_tumu(vbool8_t mask,vint32m4_t vd,int16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_tumu(vbool4_t mask,vint32m8_t vd,int16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_tumu(vbool64_t mask,vint64m1_t vd,int32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_tumu(vbool32_t mask,vint64m2_t vd,int32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_tumu(vbool16_t mask,vint64m4_t vd,int32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_tumu(vbool8_t mask,vint64m8_t vd,int32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx_tumu-2.C
new file mode 100644
index 0000000..18fc47b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx_tumu-2.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_tumu(vbool64_t mask,vint16mf4_t vd,int8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_tumu(vbool32_t mask,vint16mf2_t vd,int8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_tumu(vbool16_t mask,vint16m1_t vd,int8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_tumu(vbool8_t mask,vint16m2_t vd,int8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_tumu(vbool4_t mask,vint16m4_t vd,int8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_tumu(vbool2_t mask,vint16m8_t vd,int8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_tumu(vbool64_t mask,vint32mf2_t vd,int16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_tumu(vbool32_t mask,vint32m1_t vd,int16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_tumu(vbool16_t mask,vint32m2_t vd,int16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_tumu(vbool8_t mask,vint32m4_t vd,int16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_tumu(vbool4_t mask,vint32m8_t vd,int16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_tumu(vbool64_t mask,vint64m1_t vd,int32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_tumu(vbool32_t mask,vint64m2_t vd,int32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_tumu(vbool16_t mask,vint64m4_t vd,int32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_tumu(vbool8_t mask,vint64m8_t vd,int32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx_tumu-3.C
new file mode 100644
index 0000000..940cbdd
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx_tumu-3.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_tumu(vbool64_t mask,vint16mf4_t vd,int8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_tumu(vbool32_t mask,vint16mf2_t vd,int8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_tumu(vbool16_t mask,vint16m1_t vd,int8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_tumu(vbool8_t mask,vint16m2_t vd,int8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_tumu(vbool4_t mask,vint16m4_t vd,int8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_tumu(vbool2_t mask,vint16m8_t vd,int8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_tumu(vbool64_t mask,vint32mf2_t vd,int16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_tumu(vbool32_t mask,vint32m1_t vd,int16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_tumu(vbool16_t mask,vint32m2_t vd,int16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_tumu(vbool8_t mask,vint32m4_t vd,int16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_tumu(vbool4_t mask,vint32m8_t vd,int16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_tumu(vbool64_t mask,vint64m1_t vd,int32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_tumu(vbool32_t mask,vint64m2_t vd,int32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_tumu(vbool16_t mask,vint64m4_t vd,int32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_tumu(vbool8_t mask,vint64m8_t vd,int32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx-1.C
new file mode 100644
index 0000000..9cd1cb7
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx-1.C
@@ -0,0 +1,216 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu(vuint16mf4_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,rs1,vs2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu(vuint16mf2_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,rs1,vs2,vl);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu(vuint16m1_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,rs1,vs2,vl);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu(vuint16m2_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,rs1,vs2,vl);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu(vuint16m4_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,rs1,vs2,vl);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu(vuint16m8_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,rs1,vs2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu(vuint32mf2_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,rs1,vs2,vl);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu(vuint32m1_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,rs1,vs2,vl);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu(vuint32m2_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,rs1,vs2,vl);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu(vuint32m4_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,rs1,vs2,vl);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu(vuint32m8_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,rs1,vs2,vl);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu(vuint64m1_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,rs1,vs2,vl);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu(vuint64m2_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,rs1,vs2,vl);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu(vuint64m4_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,rs1,vs2,vl);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu(vuint64m8_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,rs1,vs2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vwmaccu(vbool64_t mask,vuint16mf4_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu(vbool32_t mask,vuint16mf2_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu(vbool16_t mask,vuint16m1_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu(vbool8_t mask,vuint16m2_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu(vbool4_t mask,vuint16m4_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu(vbool2_t mask,vuint16m8_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu(vbool64_t mask,vuint32mf2_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu(vbool32_t mask,vuint32m1_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu(vbool16_t mask,vuint32m2_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu(vbool8_t mask,vuint32m4_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu(vbool4_t mask,vuint32m8_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu(vbool64_t mask,vuint64m1_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu(vbool32_t mask,vuint64m2_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu(vbool16_t mask,vuint64m4_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu(vbool8_t mask,vuint64m8_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,rs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx-2.C
new file mode 100644
index 0000000..3b89d1a
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx-2.C
@@ -0,0 +1,216 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu(vuint16mf4_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,rs1,vs2,31);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu(vuint16mf2_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,rs1,vs2,31);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu(vuint16m1_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,rs1,vs2,31);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu(vuint16m2_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,rs1,vs2,31);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu(vuint16m4_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,rs1,vs2,31);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu(vuint16m8_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,rs1,vs2,31);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu(vuint32mf2_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,rs1,vs2,31);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu(vuint32m1_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,rs1,vs2,31);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu(vuint32m2_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,rs1,vs2,31);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu(vuint32m4_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,rs1,vs2,31);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu(vuint32m8_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,rs1,vs2,31);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu(vuint64m1_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,rs1,vs2,31);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu(vuint64m2_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,rs1,vs2,31);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu(vuint64m4_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,rs1,vs2,31);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu(vuint64m8_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,rs1,vs2,31);
+}
+
+
+vuint16mf4_t test___riscv_vwmaccu(vbool64_t mask,vuint16mf4_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu(vbool32_t mask,vuint16mf2_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu(vbool16_t mask,vuint16m1_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu(vbool8_t mask,vuint16m2_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu(vbool4_t mask,vuint16m4_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu(vbool2_t mask,vuint16m8_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu(vbool64_t mask,vuint32mf2_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu(vbool32_t mask,vuint32m1_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu(vbool16_t mask,vuint32m2_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu(vbool8_t mask,vuint32m4_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu(vbool4_t mask,vuint32m8_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu(vbool64_t mask,vuint64m1_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu(vbool32_t mask,vuint64m2_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu(vbool16_t mask,vuint64m4_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu(vbool8_t mask,vuint64m8_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,rs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx-3.C
new file mode 100644
index 0000000..94bdb41
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx-3.C
@@ -0,0 +1,216 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu(vuint16mf4_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,rs1,vs2,32);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu(vuint16mf2_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,rs1,vs2,32);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu(vuint16m1_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,rs1,vs2,32);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu(vuint16m2_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,rs1,vs2,32);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu(vuint16m4_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,rs1,vs2,32);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu(vuint16m8_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,rs1,vs2,32);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu(vuint32mf2_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,rs1,vs2,32);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu(vuint32m1_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,rs1,vs2,32);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu(vuint32m2_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,rs1,vs2,32);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu(vuint32m4_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,rs1,vs2,32);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu(vuint32m8_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,rs1,vs2,32);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu(vuint64m1_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,rs1,vs2,32);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu(vuint64m2_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,rs1,vs2,32);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu(vuint64m4_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,rs1,vs2,32);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu(vuint64m8_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,rs1,vs2,32);
+}
+
+
+vuint16mf4_t test___riscv_vwmaccu(vbool64_t mask,vuint16mf4_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu(vbool32_t mask,vuint16mf2_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu(vbool16_t mask,vuint16m1_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu(vbool8_t mask,vuint16m2_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu(vbool4_t mask,vuint16m4_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu(vbool2_t mask,vuint16m8_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu(vbool64_t mask,vuint32mf2_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu(vbool32_t mask,vuint32m1_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu(vbool16_t mask,vuint32m2_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu(vbool8_t mask,vuint32m4_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu(vbool4_t mask,vuint32m8_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu(vbool64_t mask,vuint64m1_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu(vbool32_t mask,vuint64m2_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu(vbool16_t mask,vuint64m4_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu(vbool8_t mask,vuint64m8_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,rs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx_mu-1.C
new file mode 100644
index 0000000..2bf0a54
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx_mu-1.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_mu(vbool64_t mask,vuint16mf4_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_mu(vbool32_t mask,vuint16mf2_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_mu(vbool16_t mask,vuint16m1_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_mu(vbool8_t mask,vuint16m2_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_mu(vbool4_t mask,vuint16m4_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_mu(vbool2_t mask,vuint16m8_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_mu(vbool64_t mask,vuint32mf2_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_mu(vbool32_t mask,vuint32m1_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_mu(vbool16_t mask,vuint32m2_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_mu(vbool8_t mask,vuint32m4_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_mu(vbool4_t mask,vuint32m8_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_mu(vbool64_t mask,vuint64m1_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_mu(vbool32_t mask,vuint64m2_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_mu(vbool16_t mask,vuint64m4_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_mu(vbool8_t mask,vuint64m8_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx_mu-2.C
new file mode 100644
index 0000000..7fd17ef
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx_mu-2.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_mu(vbool64_t mask,vuint16mf4_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_mu(vbool32_t mask,vuint16mf2_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_mu(vbool16_t mask,vuint16m1_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_mu(vbool8_t mask,vuint16m2_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_mu(vbool4_t mask,vuint16m4_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_mu(vbool2_t mask,vuint16m8_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_mu(vbool64_t mask,vuint32mf2_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_mu(vbool32_t mask,vuint32m1_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_mu(vbool16_t mask,vuint32m2_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_mu(vbool8_t mask,vuint32m4_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_mu(vbool4_t mask,vuint32m8_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_mu(vbool64_t mask,vuint64m1_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_mu(vbool32_t mask,vuint64m2_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_mu(vbool16_t mask,vuint64m4_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_mu(vbool8_t mask,vuint64m8_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,rs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx_mu-3.C
new file mode 100644
index 0000000..b3cce20
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx_mu-3.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_mu(vbool64_t mask,vuint16mf4_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_mu(vbool32_t mask,vuint16mf2_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_mu(vbool16_t mask,vuint16m1_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_mu(vbool8_t mask,vuint16m2_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_mu(vbool4_t mask,vuint16m4_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_mu(vbool2_t mask,vuint16m8_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_mu(vbool64_t mask,vuint32mf2_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_mu(vbool32_t mask,vuint32m1_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_mu(vbool16_t mask,vuint32m2_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_mu(vbool8_t mask,vuint32m4_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_mu(vbool4_t mask,vuint32m8_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_mu(vbool64_t mask,vuint64m1_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_mu(vbool32_t mask,vuint64m2_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_mu(vbool16_t mask,vuint64m4_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_mu(vbool8_t mask,vuint64m8_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,rs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx_tu-1.C
new file mode 100644
index 0000000..525dfb8
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx_tu-1.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_tu(vuint16mf4_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,rs1,vs2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_tu(vuint16mf2_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,rs1,vs2,vl);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_tu(vuint16m1_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,rs1,vs2,vl);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_tu(vuint16m2_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,rs1,vs2,vl);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_tu(vuint16m4_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,rs1,vs2,vl);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_tu(vuint16m8_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,rs1,vs2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_tu(vuint32mf2_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,rs1,vs2,vl);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_tu(vuint32m1_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,rs1,vs2,vl);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_tu(vuint32m2_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,rs1,vs2,vl);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_tu(vuint32m4_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,rs1,vs2,vl);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_tu(vuint32m8_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,rs1,vs2,vl);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_tu(vuint64m1_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,rs1,vs2,vl);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_tu(vuint64m2_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,rs1,vs2,vl);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_tu(vuint64m4_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,rs1,vs2,vl);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_tu(vuint64m8_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,rs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx_tu-2.C
new file mode 100644
index 0000000..8534cfa
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx_tu-2.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_tu(vuint16mf4_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,rs1,vs2,31);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_tu(vuint16mf2_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,rs1,vs2,31);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_tu(vuint16m1_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,rs1,vs2,31);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_tu(vuint16m2_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,rs1,vs2,31);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_tu(vuint16m4_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,rs1,vs2,31);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_tu(vuint16m8_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,rs1,vs2,31);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_tu(vuint32mf2_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,rs1,vs2,31);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_tu(vuint32m1_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,rs1,vs2,31);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_tu(vuint32m2_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,rs1,vs2,31);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_tu(vuint32m4_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,rs1,vs2,31);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_tu(vuint32m8_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,rs1,vs2,31);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_tu(vuint64m1_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,rs1,vs2,31);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_tu(vuint64m2_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,rs1,vs2,31);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_tu(vuint64m4_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,rs1,vs2,31);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_tu(vuint64m8_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,rs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx_tu-3.C
new file mode 100644
index 0000000..aa660c7
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx_tu-3.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_tu(vuint16mf4_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,rs1,vs2,32);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_tu(vuint16mf2_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,rs1,vs2,32);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_tu(vuint16m1_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,rs1,vs2,32);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_tu(vuint16m2_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,rs1,vs2,32);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_tu(vuint16m4_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,rs1,vs2,32);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_tu(vuint16m8_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,rs1,vs2,32);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_tu(vuint32mf2_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,rs1,vs2,32);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_tu(vuint32m1_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,rs1,vs2,32);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_tu(vuint32m2_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,rs1,vs2,32);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_tu(vuint32m4_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,rs1,vs2,32);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_tu(vuint32m8_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,rs1,vs2,32);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_tu(vuint64m1_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,rs1,vs2,32);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_tu(vuint64m2_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,rs1,vs2,32);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_tu(vuint64m4_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,rs1,vs2,32);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_tu(vuint64m8_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,rs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx_tum-1.C
new file mode 100644
index 0000000..6baf5f2
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx_tum-1.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_tum(vbool64_t mask,vuint16mf4_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_tum(vbool32_t mask,vuint16mf2_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_tum(vbool16_t mask,vuint16m1_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_tum(vbool8_t mask,vuint16m2_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_tum(vbool4_t mask,vuint16m4_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_tum(vbool2_t mask,vuint16m8_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_tum(vbool64_t mask,vuint32mf2_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_tum(vbool32_t mask,vuint32m1_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_tum(vbool16_t mask,vuint32m2_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_tum(vbool8_t mask,vuint32m4_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_tum(vbool4_t mask,vuint32m8_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_tum(vbool64_t mask,vuint64m1_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_tum(vbool32_t mask,vuint64m2_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_tum(vbool16_t mask,vuint64m4_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_tum(vbool8_t mask,vuint64m8_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx_tum-2.C
new file mode 100644
index 0000000..45a0b45
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx_tum-2.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_tum(vbool64_t mask,vuint16mf4_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_tum(vbool32_t mask,vuint16mf2_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_tum(vbool16_t mask,vuint16m1_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_tum(vbool8_t mask,vuint16m2_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_tum(vbool4_t mask,vuint16m4_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_tum(vbool2_t mask,vuint16m8_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_tum(vbool64_t mask,vuint32mf2_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_tum(vbool32_t mask,vuint32m1_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_tum(vbool16_t mask,vuint32m2_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_tum(vbool8_t mask,vuint32m4_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_tum(vbool4_t mask,vuint32m8_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_tum(vbool64_t mask,vuint64m1_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_tum(vbool32_t mask,vuint64m2_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_tum(vbool16_t mask,vuint64m4_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_tum(vbool8_t mask,vuint64m8_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,rs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx_tum-3.C
new file mode 100644
index 0000000..09ba59f
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx_tum-3.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_tum(vbool64_t mask,vuint16mf4_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_tum(vbool32_t mask,vuint16mf2_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_tum(vbool16_t mask,vuint16m1_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_tum(vbool8_t mask,vuint16m2_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_tum(vbool4_t mask,vuint16m4_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_tum(vbool2_t mask,vuint16m8_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_tum(vbool64_t mask,vuint32mf2_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_tum(vbool32_t mask,vuint32m1_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_tum(vbool16_t mask,vuint32m2_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_tum(vbool8_t mask,vuint32m4_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_tum(vbool4_t mask,vuint32m8_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_tum(vbool64_t mask,vuint64m1_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_tum(vbool32_t mask,vuint64m2_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_tum(vbool16_t mask,vuint64m4_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_tum(vbool8_t mask,vuint64m8_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,rs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx_tumu-1.C
new file mode 100644
index 0000000..c6d88e0
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx_tumu-1.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_tumu(vbool64_t mask,vuint16mf4_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_tumu(vbool32_t mask,vuint16mf2_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_tumu(vbool16_t mask,vuint16m1_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_tumu(vbool8_t mask,vuint16m2_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_tumu(vbool4_t mask,vuint16m4_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_tumu(vbool2_t mask,vuint16m8_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_tumu(vbool64_t mask,vuint32mf2_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_tumu(vbool32_t mask,vuint32m1_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_tumu(vbool16_t mask,vuint32m2_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_tumu(vbool8_t mask,vuint32m4_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_tumu(vbool4_t mask,vuint32m8_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_tumu(vbool64_t mask,vuint64m1_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_tumu(vbool32_t mask,vuint64m2_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_tumu(vbool16_t mask,vuint64m4_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_tumu(vbool8_t mask,vuint64m8_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx_tumu-2.C
new file mode 100644
index 0000000..aed3750
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx_tumu-2.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_tumu(vbool64_t mask,vuint16mf4_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_tumu(vbool32_t mask,vuint16mf2_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_tumu(vbool16_t mask,vuint16m1_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_tumu(vbool8_t mask,vuint16m2_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_tumu(vbool4_t mask,vuint16m4_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_tumu(vbool2_t mask,vuint16m8_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_tumu(vbool64_t mask,vuint32mf2_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_tumu(vbool32_t mask,vuint32m1_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_tumu(vbool16_t mask,vuint32m2_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_tumu(vbool8_t mask,vuint32m4_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_tumu(vbool4_t mask,vuint32m8_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_tumu(vbool64_t mask,vuint64m1_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_tumu(vbool32_t mask,vuint64m2_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_tumu(vbool16_t mask,vuint64m4_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_tumu(vbool8_t mask,vuint64m8_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx_tumu-3.C
new file mode 100644
index 0000000..e4c2340
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx_tumu-3.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_tumu(vbool64_t mask,vuint16mf4_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_tumu(vbool32_t mask,vuint16mf2_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_tumu(vbool16_t mask,vuint16m1_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_tumu(vbool8_t mask,vuint16m2_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_tumu(vbool4_t mask,vuint16m4_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_tumu(vbool2_t mask,vuint16m8_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_tumu(vbool64_t mask,vuint32mf2_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_tumu(vbool32_t mask,vuint32m1_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_tumu(vbool16_t mask,vuint32m2_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_tumu(vbool8_t mask,vuint32m4_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_tumu(vbool4_t mask,vuint32m8_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_tumu(vbool64_t mask,vuint64m1_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_tumu(vbool32_t mask,vuint64m2_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_tumu(vbool16_t mask,vuint64m4_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_tumu(vbool8_t mask,vuint64m8_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx-1.C
new file mode 100644
index 0000000..cb72cc3
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx-1.C
@@ -0,0 +1,216 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccus(vint16mf4_t vd,uint8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(vd,rs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmaccus(vint16mf2_t vd,uint8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(vd,rs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmaccus(vint16m1_t vd,uint8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(vd,rs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmaccus(vint16m2_t vd,uint8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(vd,rs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmaccus(vint16m4_t vd,uint8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(vd,rs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmaccus(vint16m8_t vd,uint8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(vd,rs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmaccus(vint32mf2_t vd,uint16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(vd,rs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmaccus(vint32m1_t vd,uint16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(vd,rs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmaccus(vint32m2_t vd,uint16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(vd,rs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmaccus(vint32m4_t vd,uint16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(vd,rs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmaccus(vint32m8_t vd,uint16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(vd,rs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmaccus(vint64m1_t vd,uint32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(vd,rs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmaccus(vint64m2_t vd,uint32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(vd,rs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmaccus(vint64m4_t vd,uint32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(vd,rs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmaccus(vint64m8_t vd,uint32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(vd,rs1,vs2,vl);
+}
+
+
+vint16mf4_t test___riscv_vwmaccus(vbool64_t mask,vint16mf4_t vd,uint8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmaccus(vbool32_t mask,vint16mf2_t vd,uint8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmaccus(vbool16_t mask,vint16m1_t vd,uint8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmaccus(vbool8_t mask,vint16m2_t vd,uint8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmaccus(vbool4_t mask,vint16m4_t vd,uint8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmaccus(vbool2_t mask,vint16m8_t vd,uint8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmaccus(vbool64_t mask,vint32mf2_t vd,uint16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmaccus(vbool32_t mask,vint32m1_t vd,uint16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmaccus(vbool16_t mask,vint32m2_t vd,uint16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmaccus(vbool8_t mask,vint32m4_t vd,uint16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmaccus(vbool4_t mask,vint32m8_t vd,uint16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmaccus(vbool64_t mask,vint64m1_t vd,uint32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmaccus(vbool32_t mask,vint64m2_t vd,uint32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmaccus(vbool16_t mask,vint64m4_t vd,uint32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmaccus(vbool8_t mask,vint64m8_t vd,uint32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(mask,vd,rs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx-2.C
new file mode 100644
index 0000000..4ec61a1
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx-2.C
@@ -0,0 +1,216 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccus(vint16mf4_t vd,uint8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(vd,rs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmaccus(vint16mf2_t vd,uint8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(vd,rs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmaccus(vint16m1_t vd,uint8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(vd,rs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmaccus(vint16m2_t vd,uint8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(vd,rs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmaccus(vint16m4_t vd,uint8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(vd,rs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmaccus(vint16m8_t vd,uint8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(vd,rs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmaccus(vint32mf2_t vd,uint16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(vd,rs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmaccus(vint32m1_t vd,uint16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(vd,rs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmaccus(vint32m2_t vd,uint16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(vd,rs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmaccus(vint32m4_t vd,uint16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(vd,rs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmaccus(vint32m8_t vd,uint16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(vd,rs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmaccus(vint64m1_t vd,uint32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(vd,rs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmaccus(vint64m2_t vd,uint32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(vd,rs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmaccus(vint64m4_t vd,uint32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(vd,rs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmaccus(vint64m8_t vd,uint32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(vd,rs1,vs2,31);
+}
+
+
+vint16mf4_t test___riscv_vwmaccus(vbool64_t mask,vint16mf4_t vd,uint8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(mask,vd,rs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmaccus(vbool32_t mask,vint16mf2_t vd,uint8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmaccus(vbool16_t mask,vint16m1_t vd,uint8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmaccus(vbool8_t mask,vint16m2_t vd,uint8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmaccus(vbool4_t mask,vint16m4_t vd,uint8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmaccus(vbool2_t mask,vint16m8_t vd,uint8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(mask,vd,rs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmaccus(vbool64_t mask,vint32mf2_t vd,uint16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmaccus(vbool32_t mask,vint32m1_t vd,uint16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmaccus(vbool16_t mask,vint32m2_t vd,uint16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmaccus(vbool8_t mask,vint32m4_t vd,uint16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmaccus(vbool4_t mask,vint32m8_t vd,uint16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmaccus(vbool64_t mask,vint64m1_t vd,uint32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmaccus(vbool32_t mask,vint64m2_t vd,uint32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmaccus(vbool16_t mask,vint64m4_t vd,uint32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmaccus(vbool8_t mask,vint64m8_t vd,uint32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(mask,vd,rs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx-3.C
new file mode 100644
index 0000000..1bb984c
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx-3.C
@@ -0,0 +1,216 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccus(vint16mf4_t vd,uint8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(vd,rs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmaccus(vint16mf2_t vd,uint8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(vd,rs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmaccus(vint16m1_t vd,uint8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(vd,rs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmaccus(vint16m2_t vd,uint8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(vd,rs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmaccus(vint16m4_t vd,uint8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(vd,rs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmaccus(vint16m8_t vd,uint8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(vd,rs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmaccus(vint32mf2_t vd,uint16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(vd,rs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmaccus(vint32m1_t vd,uint16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(vd,rs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmaccus(vint32m2_t vd,uint16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(vd,rs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmaccus(vint32m4_t vd,uint16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(vd,rs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmaccus(vint32m8_t vd,uint16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(vd,rs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmaccus(vint64m1_t vd,uint32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(vd,rs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmaccus(vint64m2_t vd,uint32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(vd,rs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmaccus(vint64m4_t vd,uint32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(vd,rs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmaccus(vint64m8_t vd,uint32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(vd,rs1,vs2,32);
+}
+
+
+vint16mf4_t test___riscv_vwmaccus(vbool64_t mask,vint16mf4_t vd,uint8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(mask,vd,rs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmaccus(vbool32_t mask,vint16mf2_t vd,uint8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmaccus(vbool16_t mask,vint16m1_t vd,uint8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmaccus(vbool8_t mask,vint16m2_t vd,uint8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmaccus(vbool4_t mask,vint16m4_t vd,uint8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmaccus(vbool2_t mask,vint16m8_t vd,uint8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(mask,vd,rs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmaccus(vbool64_t mask,vint32mf2_t vd,uint16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmaccus(vbool32_t mask,vint32m1_t vd,uint16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmaccus(vbool16_t mask,vint32m2_t vd,uint16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmaccus(vbool8_t mask,vint32m4_t vd,uint16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmaccus(vbool4_t mask,vint32m8_t vd,uint16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmaccus(vbool64_t mask,vint64m1_t vd,uint32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmaccus(vbool32_t mask,vint64m2_t vd,uint32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmaccus(vbool16_t mask,vint64m4_t vd,uint32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmaccus(vbool8_t mask,vint64m8_t vd,uint32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus(mask,vd,rs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx_mu-1.C
new file mode 100644
index 0000000..ed3dd61
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx_mu-1.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccus_mu(vbool64_t mask,vint16mf4_t vd,uint8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmaccus_mu(vbool32_t mask,vint16mf2_t vd,uint8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmaccus_mu(vbool16_t mask,vint16m1_t vd,uint8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmaccus_mu(vbool8_t mask,vint16m2_t vd,uint8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmaccus_mu(vbool4_t mask,vint16m4_t vd,uint8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmaccus_mu(vbool2_t mask,vint16m8_t vd,uint8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmaccus_mu(vbool64_t mask,vint32mf2_t vd,uint16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmaccus_mu(vbool32_t mask,vint32m1_t vd,uint16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmaccus_mu(vbool16_t mask,vint32m2_t vd,uint16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmaccus_mu(vbool8_t mask,vint32m4_t vd,uint16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmaccus_mu(vbool4_t mask,vint32m8_t vd,uint16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmaccus_mu(vbool64_t mask,vint64m1_t vd,uint32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmaccus_mu(vbool32_t mask,vint64m2_t vd,uint32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmaccus_mu(vbool16_t mask,vint64m4_t vd,uint32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmaccus_mu(vbool8_t mask,vint64m8_t vd,uint32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx_mu-2.C
new file mode 100644
index 0000000..1a40d88
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx_mu-2.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccus_mu(vbool64_t mask,vint16mf4_t vd,uint8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmaccus_mu(vbool32_t mask,vint16mf2_t vd,uint8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmaccus_mu(vbool16_t mask,vint16m1_t vd,uint8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmaccus_mu(vbool8_t mask,vint16m2_t vd,uint8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmaccus_mu(vbool4_t mask,vint16m4_t vd,uint8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmaccus_mu(vbool2_t mask,vint16m8_t vd,uint8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmaccus_mu(vbool64_t mask,vint32mf2_t vd,uint16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmaccus_mu(vbool32_t mask,vint32m1_t vd,uint16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmaccus_mu(vbool16_t mask,vint32m2_t vd,uint16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmaccus_mu(vbool8_t mask,vint32m4_t vd,uint16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmaccus_mu(vbool4_t mask,vint32m8_t vd,uint16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmaccus_mu(vbool64_t mask,vint64m1_t vd,uint32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmaccus_mu(vbool32_t mask,vint64m2_t vd,uint32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmaccus_mu(vbool16_t mask,vint64m4_t vd,uint32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmaccus_mu(vbool8_t mask,vint64m8_t vd,uint32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_mu(mask,vd,rs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx_mu-3.C
new file mode 100644
index 0000000..739bafc
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx_mu-3.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccus_mu(vbool64_t mask,vint16mf4_t vd,uint8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmaccus_mu(vbool32_t mask,vint16mf2_t vd,uint8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmaccus_mu(vbool16_t mask,vint16m1_t vd,uint8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmaccus_mu(vbool8_t mask,vint16m2_t vd,uint8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmaccus_mu(vbool4_t mask,vint16m4_t vd,uint8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmaccus_mu(vbool2_t mask,vint16m8_t vd,uint8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmaccus_mu(vbool64_t mask,vint32mf2_t vd,uint16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmaccus_mu(vbool32_t mask,vint32m1_t vd,uint16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmaccus_mu(vbool16_t mask,vint32m2_t vd,uint16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmaccus_mu(vbool8_t mask,vint32m4_t vd,uint16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmaccus_mu(vbool4_t mask,vint32m8_t vd,uint16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmaccus_mu(vbool64_t mask,vint64m1_t vd,uint32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmaccus_mu(vbool32_t mask,vint64m2_t vd,uint32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmaccus_mu(vbool16_t mask,vint64m4_t vd,uint32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmaccus_mu(vbool8_t mask,vint64m8_t vd,uint32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_mu(mask,vd,rs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx_tu-1.C
new file mode 100644
index 0000000..3b660db
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx_tu-1.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccus_tu(vint16mf4_t vd,uint8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tu(vd,rs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmaccus_tu(vint16mf2_t vd,uint8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tu(vd,rs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmaccus_tu(vint16m1_t vd,uint8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tu(vd,rs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmaccus_tu(vint16m2_t vd,uint8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tu(vd,rs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmaccus_tu(vint16m4_t vd,uint8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tu(vd,rs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmaccus_tu(vint16m8_t vd,uint8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tu(vd,rs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmaccus_tu(vint32mf2_t vd,uint16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tu(vd,rs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmaccus_tu(vint32m1_t vd,uint16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tu(vd,rs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmaccus_tu(vint32m2_t vd,uint16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tu(vd,rs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmaccus_tu(vint32m4_t vd,uint16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tu(vd,rs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmaccus_tu(vint32m8_t vd,uint16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tu(vd,rs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmaccus_tu(vint64m1_t vd,uint32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tu(vd,rs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmaccus_tu(vint64m2_t vd,uint32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tu(vd,rs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmaccus_tu(vint64m4_t vd,uint32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tu(vd,rs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmaccus_tu(vint64m8_t vd,uint32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tu(vd,rs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx_tu-2.C
new file mode 100644
index 0000000..a22fe1f
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx_tu-2.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccus_tu(vint16mf4_t vd,uint8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tu(vd,rs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmaccus_tu(vint16mf2_t vd,uint8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tu(vd,rs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmaccus_tu(vint16m1_t vd,uint8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tu(vd,rs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmaccus_tu(vint16m2_t vd,uint8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tu(vd,rs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmaccus_tu(vint16m4_t vd,uint8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tu(vd,rs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmaccus_tu(vint16m8_t vd,uint8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tu(vd,rs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmaccus_tu(vint32mf2_t vd,uint16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tu(vd,rs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmaccus_tu(vint32m1_t vd,uint16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tu(vd,rs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmaccus_tu(vint32m2_t vd,uint16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tu(vd,rs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmaccus_tu(vint32m4_t vd,uint16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tu(vd,rs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmaccus_tu(vint32m8_t vd,uint16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tu(vd,rs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmaccus_tu(vint64m1_t vd,uint32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tu(vd,rs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmaccus_tu(vint64m2_t vd,uint32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tu(vd,rs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmaccus_tu(vint64m4_t vd,uint32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tu(vd,rs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmaccus_tu(vint64m8_t vd,uint32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tu(vd,rs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx_tu-3.C
new file mode 100644
index 0000000..4f5b873
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx_tu-3.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccus_tu(vint16mf4_t vd,uint8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tu(vd,rs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmaccus_tu(vint16mf2_t vd,uint8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tu(vd,rs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmaccus_tu(vint16m1_t vd,uint8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tu(vd,rs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmaccus_tu(vint16m2_t vd,uint8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tu(vd,rs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmaccus_tu(vint16m4_t vd,uint8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tu(vd,rs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmaccus_tu(vint16m8_t vd,uint8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tu(vd,rs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmaccus_tu(vint32mf2_t vd,uint16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tu(vd,rs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmaccus_tu(vint32m1_t vd,uint16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tu(vd,rs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmaccus_tu(vint32m2_t vd,uint16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tu(vd,rs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmaccus_tu(vint32m4_t vd,uint16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tu(vd,rs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmaccus_tu(vint32m8_t vd,uint16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tu(vd,rs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmaccus_tu(vint64m1_t vd,uint32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tu(vd,rs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmaccus_tu(vint64m2_t vd,uint32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tu(vd,rs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmaccus_tu(vint64m4_t vd,uint32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tu(vd,rs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmaccus_tu(vint64m8_t vd,uint32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tu(vd,rs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx_tum-1.C
new file mode 100644
index 0000000..c244edc0
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx_tum-1.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccus_tum(vbool64_t mask,vint16mf4_t vd,uint8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmaccus_tum(vbool32_t mask,vint16mf2_t vd,uint8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmaccus_tum(vbool16_t mask,vint16m1_t vd,uint8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmaccus_tum(vbool8_t mask,vint16m2_t vd,uint8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmaccus_tum(vbool4_t mask,vint16m4_t vd,uint8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmaccus_tum(vbool2_t mask,vint16m8_t vd,uint8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmaccus_tum(vbool64_t mask,vint32mf2_t vd,uint16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmaccus_tum(vbool32_t mask,vint32m1_t vd,uint16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmaccus_tum(vbool16_t mask,vint32m2_t vd,uint16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmaccus_tum(vbool8_t mask,vint32m4_t vd,uint16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmaccus_tum(vbool4_t mask,vint32m8_t vd,uint16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmaccus_tum(vbool64_t mask,vint64m1_t vd,uint32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmaccus_tum(vbool32_t mask,vint64m2_t vd,uint32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmaccus_tum(vbool16_t mask,vint64m4_t vd,uint32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmaccus_tum(vbool8_t mask,vint64m8_t vd,uint32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx_tum-2.C
new file mode 100644
index 0000000..51ba824
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx_tum-2.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccus_tum(vbool64_t mask,vint16mf4_t vd,uint8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmaccus_tum(vbool32_t mask,vint16mf2_t vd,uint8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmaccus_tum(vbool16_t mask,vint16m1_t vd,uint8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmaccus_tum(vbool8_t mask,vint16m2_t vd,uint8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmaccus_tum(vbool4_t mask,vint16m4_t vd,uint8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmaccus_tum(vbool2_t mask,vint16m8_t vd,uint8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmaccus_tum(vbool64_t mask,vint32mf2_t vd,uint16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmaccus_tum(vbool32_t mask,vint32m1_t vd,uint16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmaccus_tum(vbool16_t mask,vint32m2_t vd,uint16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmaccus_tum(vbool8_t mask,vint32m4_t vd,uint16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmaccus_tum(vbool4_t mask,vint32m8_t vd,uint16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmaccus_tum(vbool64_t mask,vint64m1_t vd,uint32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmaccus_tum(vbool32_t mask,vint64m2_t vd,uint32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmaccus_tum(vbool16_t mask,vint64m4_t vd,uint32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmaccus_tum(vbool8_t mask,vint64m8_t vd,uint32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tum(mask,vd,rs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx_tum-3.C
new file mode 100644
index 0000000..95829b5
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx_tum-3.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccus_tum(vbool64_t mask,vint16mf4_t vd,uint8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmaccus_tum(vbool32_t mask,vint16mf2_t vd,uint8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmaccus_tum(vbool16_t mask,vint16m1_t vd,uint8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmaccus_tum(vbool8_t mask,vint16m2_t vd,uint8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmaccus_tum(vbool4_t mask,vint16m4_t vd,uint8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmaccus_tum(vbool2_t mask,vint16m8_t vd,uint8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmaccus_tum(vbool64_t mask,vint32mf2_t vd,uint16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmaccus_tum(vbool32_t mask,vint32m1_t vd,uint16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmaccus_tum(vbool16_t mask,vint32m2_t vd,uint16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmaccus_tum(vbool8_t mask,vint32m4_t vd,uint16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmaccus_tum(vbool4_t mask,vint32m8_t vd,uint16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmaccus_tum(vbool64_t mask,vint64m1_t vd,uint32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmaccus_tum(vbool32_t mask,vint64m2_t vd,uint32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmaccus_tum(vbool16_t mask,vint64m4_t vd,uint32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmaccus_tum(vbool8_t mask,vint64m8_t vd,uint32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tum(mask,vd,rs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx_tumu-1.C
new file mode 100644
index 0000000..f3f1281
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx_tumu-1.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccus_tumu(vbool64_t mask,vint16mf4_t vd,uint8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmaccus_tumu(vbool32_t mask,vint16mf2_t vd,uint8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmaccus_tumu(vbool16_t mask,vint16m1_t vd,uint8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmaccus_tumu(vbool8_t mask,vint16m2_t vd,uint8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmaccus_tumu(vbool4_t mask,vint16m4_t vd,uint8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmaccus_tumu(vbool2_t mask,vint16m8_t vd,uint8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmaccus_tumu(vbool64_t mask,vint32mf2_t vd,uint16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmaccus_tumu(vbool32_t mask,vint32m1_t vd,uint16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmaccus_tumu(vbool16_t mask,vint32m2_t vd,uint16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmaccus_tumu(vbool8_t mask,vint32m4_t vd,uint16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmaccus_tumu(vbool4_t mask,vint32m8_t vd,uint16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmaccus_tumu(vbool64_t mask,vint64m1_t vd,uint32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmaccus_tumu(vbool32_t mask,vint64m2_t vd,uint32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmaccus_tumu(vbool16_t mask,vint64m4_t vd,uint32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmaccus_tumu(vbool8_t mask,vint64m8_t vd,uint32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx_tumu-2.C
new file mode 100644
index 0000000..5caced7
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx_tumu-2.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccus_tumu(vbool64_t mask,vint16mf4_t vd,uint8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmaccus_tumu(vbool32_t mask,vint16mf2_t vd,uint8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmaccus_tumu(vbool16_t mask,vint16m1_t vd,uint8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmaccus_tumu(vbool8_t mask,vint16m2_t vd,uint8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmaccus_tumu(vbool4_t mask,vint16m4_t vd,uint8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmaccus_tumu(vbool2_t mask,vint16m8_t vd,uint8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmaccus_tumu(vbool64_t mask,vint32mf2_t vd,uint16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmaccus_tumu(vbool32_t mask,vint32m1_t vd,uint16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmaccus_tumu(vbool16_t mask,vint32m2_t vd,uint16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmaccus_tumu(vbool8_t mask,vint32m4_t vd,uint16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmaccus_tumu(vbool4_t mask,vint32m8_t vd,uint16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmaccus_tumu(vbool64_t mask,vint64m1_t vd,uint32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmaccus_tumu(vbool32_t mask,vint64m2_t vd,uint32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmaccus_tumu(vbool16_t mask,vint64m4_t vd,uint32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmaccus_tumu(vbool8_t mask,vint64m8_t vd,uint32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx_tumu-3.C
new file mode 100644
index 0000000..29b7610
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx_tumu-3.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccus_tumu(vbool64_t mask,vint16mf4_t vd,uint8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmaccus_tumu(vbool32_t mask,vint16mf2_t vd,uint8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmaccus_tumu(vbool16_t mask,vint16m1_t vd,uint8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmaccus_tumu(vbool8_t mask,vint16m2_t vd,uint8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmaccus_tumu(vbool4_t mask,vint16m4_t vd,uint8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmaccus_tumu(vbool2_t mask,vint16m8_t vd,uint8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmaccus_tumu(vbool64_t mask,vint32mf2_t vd,uint16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmaccus_tumu(vbool32_t mask,vint32m1_t vd,uint16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmaccus_tumu(vbool16_t mask,vint32m2_t vd,uint16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmaccus_tumu(vbool8_t mask,vint32m4_t vd,uint16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmaccus_tumu(vbool4_t mask,vint32m8_t vd,uint16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmaccus_tumu(vbool64_t mask,vint64m1_t vd,uint32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmaccus_tumu(vbool32_t mask,vint64m2_t vd,uint32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmaccus_tumu(vbool16_t mask,vint64m4_t vd,uint32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmaccus_tumu(vbool8_t mask,vint64m8_t vd,uint32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccus_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmaccus\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */