diff options
| author | Andrea Corallo <andrea.corallo@arm.com> | 2022-11-28 17:35:24 +0100 |
|---|---|---|
| committer | Andrea Corallo <andrea.corallo@arm.com> | 2023-01-25 14:36:23 +0100 |
| commit | c3c828436e7db1787d644153fe07daf356c99f2a (patch) | |
| tree | 8127d5b3868a475266ea5b246b4619fef70bf6ac /gcc | |
| parent | 0ea30b2a83c908323d73309b6f698331607eb2e0 (diff) | |
| download | gcc-c3c828436e7db1787d644153fe07daf356c99f2a.zip gcc-c3c828436e7db1787d644153fe07daf356c99f2a.tar.gz gcc-c3c828436e7db1787d644153fe07daf356c99f2a.tar.bz2 | |
arm: improve tests for vcmulq*
gcc/testsuite/ChangeLog:
* gcc.target/arm/mve/intrinsics/vcmulq_f16.c: Use
check-function-bodies instead of scan-assembler checks. Use
extern "C" for C++ testing.
* gcc.target/arm/mve/intrinsics/vcmulq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c: Likewise.
Diffstat (limited to 'gcc')
24 files changed, 656 insertions, 74 deletions
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f16.c index 142c315..456370e 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f16.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vcmul.f16 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t a, float16x8_t b) { return vcmulq_f16 (a, b); } -/* { dg-final { scan-assembler "vcmul.f16" } } */ +/* +**foo1: +** ... +** vcmul.f16 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) +** ... +*/ float16x8_t foo1 (float16x8_t a, float16x8_t b) { return vcmulq (a, b); } -/* { dg-final { scan-assembler "vcmul.f16" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f32.c index 158d750..64db652 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vcmul.f32 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t a, float32x4_t b) { return vcmulq_f32 (a, b); } -/* { dg-final { scan-assembler "vcmul.f32" } } */ +/* +**foo1: +** ... +** vcmul.f32 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) +** ... +*/ float32x4_t foo1 (float32x4_t a, float32x4_t b) { return vcmulq (a, b); } -/* { dg-final { scan-assembler "vcmul.f32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c index b38e0d9..b60f5d7 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c @@ -1,23 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) { return vcmulq_m_f16 (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) +** ... +*/ float16x8_t foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) { return vcmulq_m (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f16" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c index 7bf6873..22157d4 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c @@ -1,23 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) { return vcmulq_m_f32 (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) +** ... +*/ float32x4_t foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) { return vcmulq_m (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c index fc7162a..f01b0f3 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vcmul.f16 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t a, float16x8_t b) { return vcmulq_rot180_f16 (a, b); } -/* { dg-final { scan-assembler "vcmul.f16" } } */ +/* +**foo1: +** ... +** vcmul.f16 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) +** ... +*/ float16x8_t foo1 (float16x8_t a, float16x8_t b) { return vcmulq_rot180 (a, b); } -/* { dg-final { scan-assembler "vcmul.f16" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c index 13a4553..537385c 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vcmul.f32 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t a, float32x4_t b) { return vcmulq_rot180_f32 (a, b); } -/* { dg-final { scan-assembler "vcmul.f32" } } */ +/* +**foo1: +** ... +** vcmul.f32 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) +** ... +*/ float32x4_t foo1 (float32x4_t a, float32x4_t b) { return vcmulq_rot180 (a, b); } -/* { dg-final { scan-assembler "vcmul.f32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c index 8767e2b..bc8692e 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c @@ -1,23 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) { return vcmulq_rot180_m_f16 (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) +** ... +*/ float16x8_t foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) { return vcmulq_rot180_m (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f16" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c index 3f95103..d2a0b6d 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c @@ -1,23 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) { return vcmulq_rot180_m_f32 (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) +** ... +*/ float32x4_t foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) { return vcmulq_rot180_m (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c index f8e835f..37d7b79 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c @@ -1,22 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t a, float16x8_t b, mve_pred16_t p) { return vcmulq_rot180_x_f16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) +** ... +*/ float16x8_t foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) { return vcmulq_rot180_x (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c index d0d30c5..1e57fba 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c @@ -1,22 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t a, float32x4_t b, mve_pred16_t p) { return vcmulq_rot180_x_f32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) +** ... +*/ float32x4_t foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) { return vcmulq_rot180_x (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c index 225b8910..05c444a 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vcmul.f16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t a, float16x8_t b) { return vcmulq_rot270_f16 (a, b); } -/* { dg-final { scan-assembler "vcmul.f16" } } */ +/* +**foo1: +** ... +** vcmul.f16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) +** ... +*/ float16x8_t foo1 (float16x8_t a, float16x8_t b) { return vcmulq_rot270 (a, b); } -/* { dg-final { scan-assembler "vcmul.f16" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c index 1c8b0eb..b599c9f 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vcmul.f32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t a, float32x4_t b) { return vcmulq_rot270_f32 (a, b); } -/* { dg-final { scan-assembler "vcmul.f32" } } */ +/* +**foo1: +** ... +** vcmul.f32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) +** ... +*/ float32x4_t foo1 (float32x4_t a, float32x4_t b) { return vcmulq_rot270 (a, b); } -/* { dg-final { scan-assembler "vcmul.f32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c index 20ccb5e..fded8a0 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c @@ -1,23 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) { return vcmulq_rot270_m_f16 (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) +** ... +*/ float16x8_t foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) { return vcmulq_rot270_m (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f16" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c index 7499f42..54d939e 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c @@ -1,23 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) { return vcmulq_rot270_m_f32 (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) +** ... +*/ float32x4_t foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) { return vcmulq_rot270_m (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c index d1b52e7..d1e58cb 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c @@ -1,22 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t a, float16x8_t b, mve_pred16_t p) { return vcmulq_rot270_x_f16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) +** ... +*/ float16x8_t foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) { return vcmulq_rot270_x (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c index 35da593..07c781f 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c @@ -1,22 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t a, float32x4_t b, mve_pred16_t p) { return vcmulq_rot270_x_f32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) +** ... +*/ float32x4_t foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) { return vcmulq_rot270_x (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c index 17f96cb..53b1930 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vcmul.f16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t a, float16x8_t b) { return vcmulq_rot90_f16 (a, b); } -/* { dg-final { scan-assembler "vcmul.f16" } } */ +/* +**foo1: +** ... +** vcmul.f16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) +** ... +*/ float16x8_t foo1 (float16x8_t a, float16x8_t b) { return vcmulq_rot90 (a, b); } -/* { dg-final { scan-assembler "vcmul.f16" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c index 739fc9c..147f180 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vcmul.f32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t a, float32x4_t b) { return vcmulq_rot90_f32 (a, b); } -/* { dg-final { scan-assembler "vcmul.f32" } } */ +/* +**foo1: +** ... +** vcmul.f32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) +** ... +*/ float32x4_t foo1 (float32x4_t a, float32x4_t b) { return vcmulq_rot90 (a, b); } -/* { dg-final { scan-assembler "vcmul.f32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c index 8259baa..8c4b090 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c @@ -1,23 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) { return vcmulq_rot90_m_f16 (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) +** ... +*/ float16x8_t foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) { return vcmulq_rot90_m (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f16" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c index 751a9a6..b3131a5 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c @@ -1,23 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) { return vcmulq_rot90_m_f32 (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) +** ... +*/ float32x4_t foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) { return vcmulq_rot90_m (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c index c4aef6c..0006103 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c @@ -1,23 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t a, float16x8_t b, mve_pred16_t p) { return vcmulq_rot90_x_f16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) +** ... +*/ float16x8_t foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) { return vcmulq_rot90_x (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f16" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c index 9c54f08..8e31ad5 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c @@ -1,23 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t a, float32x4_t b, mve_pred16_t p) { return vcmulq_rot90_x_f32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) +** ... +*/ float32x4_t foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) { return vcmulq_rot90_x (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c index 7634d61..b533247 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c @@ -1,22 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t a, float16x8_t b, mve_pred16_t p) { return vcmulq_x_f16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) +** ... +*/ float16x8_t foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) { return vcmulq_x (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c index 21b6acf..a73482a 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c @@ -1,22 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t a, float32x4_t b, mve_pred16_t p) { return vcmulq_x_f32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmult.f32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) +** ... +*/ float32x4_t foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) { return vcmulq_x (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file |