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| author | Matthew Fortune <matthew.fortune@imgtec.com> | 2017-03-31 09:21:57 +0000 |
|---|---|---|
| committer | Matthew Fortune <mpf@gcc.gnu.org> | 2017-03-31 09:21:57 +0000 |
| commit | c330f78894eea4231e7c09877cd0df4c3b1dc590 (patch) | |
| tree | fb47a3bf6add22f75a0c9956d3d8fdcbdaa873f2 /gcc | |
| parent | eceb24097b2781965126302bf60ef5273f1c4073 (diff) | |
| download | gcc-c330f78894eea4231e7c09877cd0df4c3b1dc590.zip gcc-c330f78894eea4231e7c09877cd0df4c3b1dc590.tar.gz gcc-c330f78894eea4231e7c09877cd0df4c3b1dc590.tar.bz2 | |
Fix extraction from odd-numbered MSA registers
This fixes a build-failure with gcc.c-torture/execute/20050604-1.c when
using -mabi=32 -mmsa -mno-odd-spreg.
gcc/
* config/mips/mips-msa.md (msa_vec_extract_<msafmt_f>): Update
extraction from odd-numbered MSA register.
From-SVN: r246613
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/mips/mips-msa.md | 15 |
2 files changed, 19 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ba4f7fd..594b32a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2017-03-31 Matthew Fortune <matthew.fortune@imgtec.com> + + * config/mips/mips-msa.md (msa_vec_extract_<msafmt_f>): Update + extraction from odd-numbered MSA register. + 2017-03-31 Jakub Jelinek <jakub@redhat.com> PR middle-end/80173 diff --git a/gcc/config/mips/mips-msa.md b/gcc/config/mips/mips-msa.md index accb8de..c80be47 100644 --- a/gcc/config/mips/mips-msa.md +++ b/gcc/config/mips/mips-msa.md @@ -366,7 +366,20 @@ "#" "&& reload_completed" [(set (match_dup 0) (match_dup 1))] - "operands[1] = gen_rtx_REG (<UNITMODE>mode, REGNO (operands[1]));" +{ + /* An MSA register cannot be reinterpreted as a single precision + register when using -mno-odd-spreg and the MSA register is + an odd number. */ + if (<UNITMODE>mode == SFmode && !TARGET_ODD_SPREG + && (REGNO (operands[1]) & 1)) + { + emit_move_insn (gen_rtx_REG (<MODE>mode, REGNO (operands[0])), + operands[1]); + operands[1] = operands[0]; + } + else + operands[1] = gen_rtx_REG (<UNITMODE>mode, REGNO (operands[1])); +} [(set_attr "move_type" "fmove") (set_attr "mode" "<UNITMODE>")]) |