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authorSimplyTheOther <simplytheother@gmail.com>2020-08-07 22:35:45 +0800
committerPhilip Herron <philip.herron@embecosm.com>2020-11-28 21:13:20 +0000
commitc26f60f6a28394e98ac1d830cbe8f632ef576dbb (patch)
tree8a55e520ae319b1f4e9c9e88b73e3669960b2ee3 /gcc
parent9dd2cdd8338fd835a227521661eafe259e401830 (diff)
downloadgcc-c26f60f6a28394e98ac1d830cbe8f632ef576dbb.zip
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Miscellaneous improvements to various target hooks
Diffstat (limited to 'gcc')
-rw-r--r--gcc/config/bfin/bfin.h1177
-rw-r--r--gcc/config/c6x/c6x-rust.c1
-rw-r--r--gcc/config/cr16/cr16-rust.c1
-rw-r--r--gcc/config/csky/csky-rust.c1
-rw-r--r--gcc/config/epiphany/epiphany-rust.c1
-rw-r--r--gcc/config/frv/frv-rust.c1
-rw-r--r--gcc/config/ft32/ft32.h3
-rw-r--r--gcc/config/ia64/ia64-rust.c2
8 files changed, 638 insertions, 549 deletions
diff --git a/gcc/config/bfin/bfin.h b/gcc/config/bfin/bfin.h
index 0ebdc45..3ac6444 100644
--- a/gcc/config/bfin/bfin.h
+++ b/gcc/config/bfin/bfin.h
@@ -32,186 +32,221 @@
/* Predefinition in the preprocessor for this target machine */
#ifndef TARGET_CPU_CPP_BUILTINS
-#define TARGET_CPU_CPP_BUILTINS() \
- do \
- { \
- builtin_define_std ("bfin"); \
- builtin_define_std ("BFIN"); \
- builtin_define ("__ADSPBLACKFIN__"); \
- builtin_define ("__ADSPLPBLACKFIN__"); \
- \
- switch (bfin_cpu_type) \
- { \
- case BFIN_CPU_UNKNOWN: \
- break; \
- case BFIN_CPU_BF512: \
- builtin_define ("__ADSPBF512__"); \
- builtin_define ("__ADSPBF51x__"); \
- break; \
- case BFIN_CPU_BF514: \
- builtin_define ("__ADSPBF514__"); \
- builtin_define ("__ADSPBF51x__"); \
- break; \
- case BFIN_CPU_BF516: \
- builtin_define ("__ADSPBF516__"); \
- builtin_define ("__ADSPBF51x__"); \
- break; \
- case BFIN_CPU_BF518: \
- builtin_define ("__ADSPBF518__"); \
- builtin_define ("__ADSPBF51x__"); \
- break; \
- case BFIN_CPU_BF522: \
- builtin_define ("__ADSPBF522__"); \
- builtin_define ("__ADSPBF52x__"); \
- break; \
- case BFIN_CPU_BF523: \
- builtin_define ("__ADSPBF523__"); \
- builtin_define ("__ADSPBF52x__"); \
- break; \
- case BFIN_CPU_BF524: \
- builtin_define ("__ADSPBF524__"); \
- builtin_define ("__ADSPBF52x__"); \
- break; \
- case BFIN_CPU_BF525: \
- builtin_define ("__ADSPBF525__"); \
- builtin_define ("__ADSPBF52x__"); \
- break; \
- case BFIN_CPU_BF526: \
- builtin_define ("__ADSPBF526__"); \
- builtin_define ("__ADSPBF52x__"); \
- break; \
- case BFIN_CPU_BF527: \
- builtin_define ("__ADSPBF527__"); \
- builtin_define ("__ADSPBF52x__"); \
- break; \
- case BFIN_CPU_BF531: \
- builtin_define ("__ADSPBF531__"); \
- break; \
- case BFIN_CPU_BF532: \
- builtin_define ("__ADSPBF532__"); \
- break; \
- case BFIN_CPU_BF533: \
- builtin_define ("__ADSPBF533__"); \
- break; \
- case BFIN_CPU_BF534: \
- builtin_define ("__ADSPBF534__"); \
- break; \
- case BFIN_CPU_BF536: \
- builtin_define ("__ADSPBF536__"); \
- break; \
- case BFIN_CPU_BF537: \
- builtin_define ("__ADSPBF537__"); \
- break; \
- case BFIN_CPU_BF538: \
- builtin_define ("__ADSPBF538__"); \
- break; \
- case BFIN_CPU_BF539: \
- builtin_define ("__ADSPBF539__"); \
- break; \
- case BFIN_CPU_BF542M: \
- builtin_define ("__ADSPBF542M__"); \
- /* FALLTHRU */ \
- case BFIN_CPU_BF542: \
- builtin_define ("__ADSPBF542__"); \
- builtin_define ("__ADSPBF54x__"); \
- break; \
- case BFIN_CPU_BF544M: \
- builtin_define ("__ADSPBF544M__"); \
- /* FALLTHRU */ \
- case BFIN_CPU_BF544: \
- builtin_define ("__ADSPBF544__"); \
- builtin_define ("__ADSPBF54x__"); \
- break; \
- case BFIN_CPU_BF547M: \
- builtin_define ("__ADSPBF547M__"); \
- /* FALLTHRU */ \
- case BFIN_CPU_BF547: \
- builtin_define ("__ADSPBF547__"); \
- builtin_define ("__ADSPBF54x__"); \
- break; \
- case BFIN_CPU_BF548M: \
- builtin_define ("__ADSPBF548M__"); \
- /* FALLTHRU */ \
- case BFIN_CPU_BF548: \
- builtin_define ("__ADSPBF548__"); \
- builtin_define ("__ADSPBF54x__"); \
- break; \
- case BFIN_CPU_BF549M: \
- builtin_define ("__ADSPBF549M__"); \
- /* FALLTHRU */ \
- case BFIN_CPU_BF549: \
- builtin_define ("__ADSPBF549__"); \
- builtin_define ("__ADSPBF54x__"); \
- break; \
- case BFIN_CPU_BF561: \
- builtin_define ("__ADSPBF561__"); \
- break; \
- case BFIN_CPU_BF592: \
- builtin_define ("__ADSPBF592__"); \
- builtin_define ("__ADSPBF59x__"); \
- break; \
- } \
- \
- if (bfin_si_revision != -1) \
- { \
- /* space of 0xnnnn and a NUL */ \
- char *buf = XALLOCAVEC (char, 7); \
- \
- sprintf (buf, "0x%04x", bfin_si_revision); \
- builtin_define_with_value ("__SILICON_REVISION__", buf, 0); \
- } \
- \
- if (bfin_workarounds) \
- builtin_define ("__WORKAROUNDS_ENABLED"); \
- if (ENABLE_WA_SPECULATIVE_LOADS) \
- builtin_define ("__WORKAROUND_SPECULATIVE_LOADS"); \
- if (ENABLE_WA_SPECULATIVE_SYNCS) \
- builtin_define ("__WORKAROUND_SPECULATIVE_SYNCS"); \
- if (ENABLE_WA_INDIRECT_CALLS) \
- builtin_define ("__WORKAROUND_INDIRECT_CALLS"); \
- if (ENABLE_WA_RETS) \
- builtin_define ("__WORKAROUND_RETS"); \
- \
- if (TARGET_FDPIC) \
- { \
- builtin_define ("__BFIN_FDPIC__"); \
- builtin_define ("__FDPIC__"); \
- } \
- if (TARGET_ID_SHARED_LIBRARY \
- && !TARGET_SEP_DATA) \
- builtin_define ("__ID_SHARED_LIB__"); \
- if (flag_no_builtin) \
- builtin_define ("__NO_BUILTIN"); \
- if (TARGET_MULTICORE) \
- builtin_define ("__BFIN_MULTICORE"); \
- if (TARGET_COREA) \
- builtin_define ("__BFIN_COREA"); \
- if (TARGET_COREB) \
- builtin_define ("__BFIN_COREB"); \
- if (TARGET_SDRAM) \
- builtin_define ("__BFIN_SDRAM"); \
- } \
+#define TARGET_CPU_CPP_BUILTINS() \
+ do \
+ { \
+ builtin_define_std ("bfin"); \
+ builtin_define_std ("BFIN"); \
+ builtin_define ("__ADSPBLACKFIN__"); \
+ builtin_define ("__ADSPLPBLACKFIN__"); \
+ \
+ switch (bfin_cpu_type) \
+ { \
+ case BFIN_CPU_UNKNOWN: \
+ break; \
+ case BFIN_CPU_BF512: \
+ builtin_define ("__ADSPBF512__"); \
+ builtin_define ("__ADSPBF51x__"); \
+ break; \
+ case BFIN_CPU_BF514: \
+ builtin_define ("__ADSPBF514__"); \
+ builtin_define ("__ADSPBF51x__"); \
+ break; \
+ case BFIN_CPU_BF516: \
+ builtin_define ("__ADSPBF516__"); \
+ builtin_define ("__ADSPBF51x__"); \
+ break; \
+ case BFIN_CPU_BF518: \
+ builtin_define ("__ADSPBF518__"); \
+ builtin_define ("__ADSPBF51x__"); \
+ break; \
+ case BFIN_CPU_BF522: \
+ builtin_define ("__ADSPBF522__"); \
+ builtin_define ("__ADSPBF52x__"); \
+ break; \
+ case BFIN_CPU_BF523: \
+ builtin_define ("__ADSPBF523__"); \
+ builtin_define ("__ADSPBF52x__"); \
+ break; \
+ case BFIN_CPU_BF524: \
+ builtin_define ("__ADSPBF524__"); \
+ builtin_define ("__ADSPBF52x__"); \
+ break; \
+ case BFIN_CPU_BF525: \
+ builtin_define ("__ADSPBF525__"); \
+ builtin_define ("__ADSPBF52x__"); \
+ break; \
+ case BFIN_CPU_BF526: \
+ builtin_define ("__ADSPBF526__"); \
+ builtin_define ("__ADSPBF52x__"); \
+ break; \
+ case BFIN_CPU_BF527: \
+ builtin_define ("__ADSPBF527__"); \
+ builtin_define ("__ADSPBF52x__"); \
+ break; \
+ case BFIN_CPU_BF531: \
+ builtin_define ("__ADSPBF531__"); \
+ break; \
+ case BFIN_CPU_BF532: \
+ builtin_define ("__ADSPBF532__"); \
+ break; \
+ case BFIN_CPU_BF533: \
+ builtin_define ("__ADSPBF533__"); \
+ break; \
+ case BFIN_CPU_BF534: \
+ builtin_define ("__ADSPBF534__"); \
+ break; \
+ case BFIN_CPU_BF536: \
+ builtin_define ("__ADSPBF536__"); \
+ break; \
+ case BFIN_CPU_BF537: \
+ builtin_define ("__ADSPBF537__"); \
+ break; \
+ case BFIN_CPU_BF538: \
+ builtin_define ("__ADSPBF538__"); \
+ break; \
+ case BFIN_CPU_BF539: \
+ builtin_define ("__ADSPBF539__"); \
+ break; \
+ case BFIN_CPU_BF542M: \
+ builtin_define ("__ADSPBF542M__"); \
+ /* FALLTHRU */ \
+ case BFIN_CPU_BF542: \
+ builtin_define ("__ADSPBF542__"); \
+ builtin_define ("__ADSPBF54x__"); \
+ break; \
+ case BFIN_CPU_BF544M: \
+ builtin_define ("__ADSPBF544M__"); \
+ /* FALLTHRU */ \
+ case BFIN_CPU_BF544: \
+ builtin_define ("__ADSPBF544__"); \
+ builtin_define ("__ADSPBF54x__"); \
+ break; \
+ case BFIN_CPU_BF547M: \
+ builtin_define ("__ADSPBF547M__"); \
+ /* FALLTHRU */ \
+ case BFIN_CPU_BF547: \
+ builtin_define ("__ADSPBF547__"); \
+ builtin_define ("__ADSPBF54x__"); \
+ break; \
+ case BFIN_CPU_BF548M: \
+ builtin_define ("__ADSPBF548M__"); \
+ /* FALLTHRU */ \
+ case BFIN_CPU_BF548: \
+ builtin_define ("__ADSPBF548__"); \
+ builtin_define ("__ADSPBF54x__"); \
+ break; \
+ case BFIN_CPU_BF549M: \
+ builtin_define ("__ADSPBF549M__"); \
+ /* FALLTHRU */ \
+ case BFIN_CPU_BF549: \
+ builtin_define ("__ADSPBF549__"); \
+ builtin_define ("__ADSPBF54x__"); \
+ break; \
+ case BFIN_CPU_BF561: \
+ builtin_define ("__ADSPBF561__"); \
+ break; \
+ case BFIN_CPU_BF592: \
+ builtin_define ("__ADSPBF592__"); \
+ builtin_define ("__ADSPBF59x__"); \
+ break; \
+ } \
+ \
+ if (bfin_si_revision != -1) \
+ { \
+ /* space of 0xnnnn and a NUL */ \
+ char *buf = XALLOCAVEC (char, 7); \
+ \
+ sprintf (buf, "0x%04x", bfin_si_revision); \
+ builtin_define_with_value ("__SILICON_REVISION__", buf, 0); \
+ } \
+ \
+ if (bfin_workarounds) \
+ builtin_define ("__WORKAROUNDS_ENABLED"); \
+ if (ENABLE_WA_SPECULATIVE_LOADS) \
+ builtin_define ("__WORKAROUND_SPECULATIVE_LOADS"); \
+ if (ENABLE_WA_SPECULATIVE_SYNCS) \
+ builtin_define ("__WORKAROUND_SPECULATIVE_SYNCS"); \
+ if (ENABLE_WA_INDIRECT_CALLS) \
+ builtin_define ("__WORKAROUND_INDIRECT_CALLS"); \
+ if (ENABLE_WA_RETS) \
+ builtin_define ("__WORKAROUND_RETS"); \
+ \
+ if (TARGET_FDPIC) \
+ { \
+ builtin_define ("__BFIN_FDPIC__"); \
+ builtin_define ("__FDPIC__"); \
+ } \
+ if (TARGET_ID_SHARED_LIBRARY && !TARGET_SEP_DATA) \
+ builtin_define ("__ID_SHARED_LIB__"); \
+ if (flag_no_builtin) \
+ builtin_define ("__NO_BUILTIN"); \
+ if (TARGET_MULTICORE) \
+ builtin_define ("__BFIN_MULTICORE"); \
+ if (TARGET_COREA) \
+ builtin_define ("__BFIN_COREA"); \
+ if (TARGET_COREB) \
+ builtin_define ("__BFIN_COREB"); \
+ if (TARGET_SDRAM) \
+ builtin_define ("__BFIN_SDRAM"); \
+ } \
while (0)
#endif
-#define DRIVER_SELF_SPECS SUBTARGET_DRIVER_SELF_SPECS "\
+/* Rust target CPU info for this machine. Could not add new compilation unit
+ without significant modification to target, so included as macro instead. */
+#define TARGET_RUST_CPU_INFO() \
+ do \
+ { \
+ rust_add_target_info ("target_arch", "bfin"); \
+ /* TODO maybe add other features? based on old llvm so ones missing */ \
+ if (TARGET_SDRAM) \
+ rust_add_target_info ("target_feature", "sdram"); \
+ if (TARGET_ICPLB) \
+ rust_add_target_info ("target_feature", "icplb"); \
+ if (ENABLE_WA_05000074) \
+ rust_add_target_info ("target_feature", "mi-shift-anomaly"); \
+ if (ENABLE_WA_SPECULATIVE_SYNCS) \
+ rust_add_target_info ("target_feature", "csync-anomaly"); \
+ if (ENABLE_WA_SPECULATIVE_LOADS) \
+ rust_add_target_info ("target_feature", "specld-anomaly"); \
+ if (ENABLE_WA_05000257) \
+ rust_add_target_info ("target_feature", "hwloop-anomaly"); \
+ if (ENABLE_WA_05000283) \
+ rust_add_target_info ("target_feature", "mmr-stall-anomaly"); \
+ if (ENABLE_WA_LOAD_LCREGS) \
+ rust_add_target_info ("target_feature", "lcregs-anomaly"); \
+ if (ENABLE_WA_05000315) \
+ rust_add_target_info ("target_feature", "killed-mmr-anomaly"); \
+ if (ENABLE_WA_RETS) \
+ rust_add_target_info ("target_feature", "rets-anomaly"); \
+ if (ENABLE_WA_INDIRECT_CALLS) \
+ rust_add_target_info ("target_feature", "ind-call-anomaly"); \
+ } \
+ while (0)
+
+#define DRIVER_SELF_SPECS \
+ SUBTARGET_DRIVER_SELF_SPECS "\
%{mleaf-id-shared-library:%{!mid-shared-library:-mid-shared-library}} \
%{mfdpic:%{!fpic:%{!fpie:%{!fPIC:%{!fPIE:\
%{!fno-pic:%{!fno-pie:%{!fno-PIC:%{!fno-PIE:-fpie}}}}}}}}} \
"
#ifndef SUBTARGET_DRIVER_SELF_SPECS
-# define SUBTARGET_DRIVER_SELF_SPECS
+#define SUBTARGET_DRIVER_SELF_SPECS
#endif
-#define LINK_GCC_C_SEQUENCE_SPEC "\
+#define LINK_GCC_C_SEQUENCE_SPEC \
+ "\
%{mfast-fp:-lbffastfp} %G %{!nolibc:%L} %{mfast-fp:-lbffastfp} %G \
"
-#undef ASM_SPEC
-#define ASM_SPEC "\
+#undef ASM_SPEC
+#define ASM_SPEC \
+ "\
%{mno-fdpic:-mnopic} %{mfdpic}"
-#define LINK_SPEC "\
+#define LINK_SPEC \
+ "\
%{h*} %{v:-V} \
%{mfdpic:-melf32bfinfd -z text} \
%{static:-dn -Bstatic} \
@@ -220,7 +255,7 @@
-init __init -fini __fini "
/* Generate DSP instructions, like DSP halfword loads */
-#define TARGET_DSP (1)
+#define TARGET_DSP (1)
#define TARGET_DEFAULT 0
@@ -229,8 +264,8 @@
extern const char *bfin_library_id_string;
-#define FUNCTION_MODE SImode
-#define Pmode SImode
+#define FUNCTION_MODE SImode
+#define Pmode SImode
/* store-condition-codes instructions store 0 for false
This is the value stored for true. */
@@ -273,7 +308,7 @@ extern const char *bfin_library_id_string;
#define FDPIC_FPTR_REGNO REG_P1
#define FDPIC_REGNO REG_P3
-#define OUR_FDPIC_REG get_hard_reg_initial_val (SImode, FDPIC_REGNO)
+#define OUR_FDPIC_REG get_hard_reg_initial_val (SImode, FDPIC_REGNO)
/* A static chain register for nested functions. We need to use a
call-clobbered register for this. */
@@ -295,10 +330,10 @@ extern const char *bfin_library_id_string;
/* Define this if the above stack space is to be considered part of the
* space allocated by the caller. */
#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
-
+
/* Define this if the maximum size of all the outgoing args is to be
accumulated and pushed during the prologue. The amount can be
- found in the variable crtl->outgoing_args_size. */
+ found in the variable crtl->outgoing_args_size. */
#define ACCUMULATE_OUTGOING_ARGS 1
/*#define DATA_ALIGNMENT(TYPE, BASIC-ALIGN) for arrays.. */
@@ -316,7 +351,7 @@ extern const char *bfin_library_id_string;
#define LOCAL_ALIGNMENT(TYPE, ALIGN) bfin_local_alignment ((TYPE), (ALIGN))
#define TRAMPOLINE_SIZE (TARGET_FDPIC ? 30 : 18)
-
+
/* Definitions for register eliminations.
This is an array of structures. Each structure initializes one pair
@@ -330,17 +365,21 @@ extern const char *bfin_library_id_string;
circumstances. The hard frame pointer is not used before reload and
so it is not eligible for elimination. */
-#define ELIMINABLE_REGS \
-{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
- { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
- { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} \
+#define ELIMINABLE_REGS \
+ { \
+ {ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
+ {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
+ { \
+ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM \
+ } \
+ }
/* Define the offset between two registers, one to be eliminated, and the other
its replacement, at the start of a routine. */
-#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
+#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
((OFFSET) = bfin_initial_elimination_offset ((FROM), (TO)))
-
+
/* This processor has
8 data register for doing arithmetic
8 pointer register for doing addressing, including
@@ -363,50 +402,54 @@ extern const char *bfin_library_id_string;
#define IREG_P(X) (REG_P (X) && I_REGNO_P (REGNO (X)))
#define DPREG_P(X) (REG_P (X) && DP_REGNO_P (REGNO (X)))
-#define REGISTER_NAMES { \
- "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", \
- "P0", "P1", "P2", "P3", "P4", "P5", "SP", "FP", \
- "I0", "I1", "I2", "I3", "B0", "B1", "B2", "B3", \
- "L0", "L1", "L2", "L3", "M0", "M1", "M2", "M3", \
- "A0", "A1", \
- "CC", \
- "RETS", "RETI", "RETX", "RETN", "RETE", "ASTAT", "SEQSTAT", "USP", \
- "ARGP", \
- "LT0", "LT1", "LC0", "LC1", "LB0", "LB1" \
-}
-
-#define SHORT_REGISTER_NAMES { \
- "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L", \
- "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L", \
- "I0.L", "I1.L", "I2.L", "I3.L", "B0.L", "B1.L", "B2.L", "B3.L", \
- "L0.L", "L1.L", "L2.L", "L3.L", "M0.L", "M1.L", "M2.L", "M3.L", }
-
-#define HIGH_REGISTER_NAMES { \
- "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H", \
- "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H", \
- "I0.H", "I1.H", "I2.H", "I3.H", "B0.H", "B1.H", "B2.H", "B3.H", \
- "L0.H", "L1.H", "L2.H", "L3.H", "M0.H", "M1.H", "M2.H", "M3.H", }
-
-#define DREGS_PAIR_NAMES { \
- "R1:0.p", 0, "R3:2.p", 0, "R5:4.p", 0, "R7:6.p", 0, }
-
-#define BYTE_REGISTER_NAMES { \
- "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B", }
-
+#define REGISTER_NAMES \
+ { \
+ "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", "P0", "P1", "P2", "P3", \
+ "P4", "P5", "SP", "FP", "I0", "I1", "I2", "I3", "B0", "B1", "B2", "B3", \
+ "L0", "L1", "L2", "L3", "M0", "M1", "M2", "M3", "A0", "A1", "CC", \
+ "RETS", "RETI", "RETX", "RETN", "RETE", "ASTAT", "SEQSTAT", "USP", \
+ "ARGP", "LT0", "LT1", "LC0", "LC1", "LB0", "LB1" \
+ }
+
+#define SHORT_REGISTER_NAMES \
+ { \
+ "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L", "P0.L", \
+ "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L", "I0.L", "I1.L", \
+ "I2.L", "I3.L", "B0.L", "B1.L", "B2.L", "B3.L", "L0.L", "L1.L", "L2.L", \
+ "L3.L", "M0.L", "M1.L", "M2.L", "M3.L", \
+ }
+
+#define HIGH_REGISTER_NAMES \
+ { \
+ "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H", "P0.H", \
+ "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H", "I0.H", "I1.H", \
+ "I2.H", "I3.H", "B0.H", "B1.H", "B2.H", "B3.H", "L0.H", "L1.H", "L2.H", \
+ "L3.H", "M0.H", "M1.H", "M2.H", "M3.H", \
+ }
+
+#define DREGS_PAIR_NAMES \
+ { \
+ "R1:0.p", 0, "R3:2.p", 0, "R5:4.p", 0, "R7:6.p", 0, \
+ }
+
+#define BYTE_REGISTER_NAMES \
+ { \
+ "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B", \
+ }
/* 1 for registers that have pervasive standard uses
and are not available for the register allocator. */
-#define FIXED_REGISTERS \
-/*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \
-{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
-/*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \
- 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, \
-/*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \
- 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
-/*lb0/1 */ \
- 1, 1 \
-}
+#define FIXED_REGISTERS \
+ /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \
+ { \
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
+ 0, /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \
+ 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, \
+ 0, /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \
+ 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /*lb0/1 */ \
+ 1, 1 \
+ }
/* 1 for registers not available across function calls.
These must include the FIXED_REGISTERS and also any
@@ -415,16 +458,16 @@ extern const char *bfin_library_id_string;
and the register where structure-value addresses are passed.
Aside from that, you can include as many other registers as you like. */
-#define CALL_USED_REGISTERS \
-/*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \
-{ 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 0, \
-/*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
-/*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
-/*lb0/1 */ \
- 1, 1 \
-}
+#define CALL_USED_REGISTERS \
+ /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \
+ { \
+ 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, \
+ 0, /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
+ 1, /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /*lb0/1 */ \
+ 1, 1 \
+ }
/* Order in which to allocate registers. Each register must be
listed once, even those in FIXED_REGISTERS. List frame pointer
@@ -432,17 +475,15 @@ extern const char *bfin_library_id_string;
registers listed in CALL_USED_REGISTERS, keeping the others
available for storage of persistent values. */
-#define REG_ALLOC_ORDER \
-{ REG_R0, REG_R1, REG_R2, REG_R3, REG_R7, REG_R6, REG_R5, REG_R4, \
- REG_P2, REG_P1, REG_P0, REG_P5, REG_P4, REG_P3, REG_P6, REG_P7, \
- REG_A0, REG_A1, \
- REG_I0, REG_I1, REG_I2, REG_I3, REG_B0, REG_B1, REG_B2, REG_B3, \
- REG_L0, REG_L1, REG_L2, REG_L3, REG_M0, REG_M1, REG_M2, REG_M3, \
- REG_RETS, REG_RETI, REG_RETX, REG_RETN, REG_RETE, \
- REG_ASTAT, REG_SEQSTAT, REG_USP, \
- REG_CC, REG_ARGP, \
- REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1 \
-}
+#define REG_ALLOC_ORDER \
+ { \
+ REG_R0, REG_R1, REG_R2, REG_R3, REG_R7, REG_R6, REG_R5, REG_R4, REG_P2, \
+ REG_P1, REG_P0, REG_P5, REG_P4, REG_P3, REG_P6, REG_P7, REG_A0, REG_A1, \
+ REG_I0, REG_I1, REG_I2, REG_I3, REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, \
+ REG_L1, REG_L2, REG_L3, REG_M0, REG_M1, REG_M2, REG_M3, REG_RETS, \
+ REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_ASTAT, REG_SEQSTAT, REG_USP, \
+ REG_CC, REG_ARGP, REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1 \
+ }
/* Define the classes of registers for register constraints in the
machine description. Also define ranges of constants.
@@ -464,7 +505,6 @@ extern const char *bfin_library_id_string;
For any two classes, it is very desirable that there be another
class that represents their union. */
-
enum reg_class
{
NO_REGS,
@@ -472,7 +512,8 @@ enum reg_class
BREGS,
LREGS,
MREGS,
- CIRCREGS, /* Circular buffering registers, Ix, Bx, Lx together form. See Automatic Circular Buffering. */
+ CIRCREGS, /* Circular buffering registers, Ix, Bx, Lx together form. See
+ Automatic Circular Buffering. */
DAGREGS,
EVEN_AREGS,
ODD_AREGS,
@@ -502,52 +543,25 @@ enum reg_class
LB_REGS,
PROLOGUE_REGS,
NON_A_CC_REGS,
- ALL_REGS, LIM_REG_CLASSES
+ ALL_REGS,
+ LIM_REG_CLASSES
};
-#define N_REG_CLASSES ((int)LIM_REG_CLASSES)
+#define N_REG_CLASSES ((int) LIM_REG_CLASSES)
#define GENERAL_REGS DPREGS
/* Give names of register classes as strings for dump file. */
-#define REG_CLASS_NAMES \
-{ "NO_REGS", \
- "IREGS", \
- "BREGS", \
- "LREGS", \
- "MREGS", \
- "CIRCREGS", \
- "DAGREGS", \
- "EVEN_AREGS", \
- "ODD_AREGS", \
- "AREGS", \
- "CCREGS", \
- "EVEN_DREGS", \
- "ODD_DREGS", \
- "D0REGS", \
- "D1REGS", \
- "D2REGS", \
- "D3REGS", \
- "D4REGS", \
- "D5REGS", \
- "D6REGS", \
- "D7REGS", \
- "DREGS", \
- "P0REGS", \
- "FDPIC_REGS", \
- "FDPIC_FPTR_REGS", \
- "PREGS_CLOBBERED", \
- "PREGS", \
- "IPREGS", \
- "DPREGS", \
- "MOST_REGS", \
- "LT_REGS", \
- "LC_REGS", \
- "LB_REGS", \
- "PROLOGUE_REGS", \
- "NON_A_CC_REGS", \
- "ALL_REGS" }
+#define REG_CLASS_NAMES \
+ { \
+ "NO_REGS", "IREGS", "BREGS", "LREGS", "MREGS", "CIRCREGS", "DAGREGS", \
+ "EVEN_AREGS", "ODD_AREGS", "AREGS", "CCREGS", "EVEN_DREGS", "ODD_DREGS", \
+ "D0REGS", "D1REGS", "D2REGS", "D3REGS", "D4REGS", "D5REGS", "D6REGS", \
+ "D7REGS", "DREGS", "P0REGS", "FDPIC_REGS", "FDPIC_FPTR_REGS", \
+ "PREGS_CLOBBERED", "PREGS", "IPREGS", "DPREGS", "MOST_REGS", "LT_REGS", \
+ "LC_REGS", "LB_REGS", "PROLOGUE_REGS", "NON_A_CC_REGS", "ALL_REGS" \
+ }
/* An initializer containing the contents of the register classes, as integers
which are bit masks. The Nth integer specifies the contents of class N.
@@ -563,102 +577,145 @@ enum reg_class
/* NOTE: DSP registers, IREGS - AREGS, are not GENERAL_REGS. We use
MOST_REGS as the union of DPREGS and DAGREGS. */
-#define REG_CLASS_CONTENTS \
- /* 31 - 0 63-32 */ \
-{ { 0x00000000, 0 }, /* NO_REGS */ \
- { 0x000f0000, 0 }, /* IREGS */ \
- { 0x00f00000, 0 }, /* BREGS */ \
- { 0x0f000000, 0 }, /* LREGS */ \
- { 0xf0000000, 0 }, /* MREGS */ \
- { 0x0fff0000, 0 }, /* CIRCREGS */ \
- { 0xffff0000, 0 }, /* DAGREGS */ \
- { 0x00000000, 0x1 }, /* EVEN_AREGS */ \
- { 0x00000000, 0x2 }, /* ODD_AREGS */ \
- { 0x00000000, 0x3 }, /* AREGS */ \
- { 0x00000000, 0x4 }, /* CCREGS */ \
- { 0x00000055, 0 }, /* EVEN_DREGS */ \
- { 0x000000aa, 0 }, /* ODD_DREGS */ \
- { 0x00000001, 0 }, /* D0REGS */ \
- { 0x00000002, 0 }, /* D1REGS */ \
- { 0x00000004, 0 }, /* D2REGS */ \
- { 0x00000008, 0 }, /* D3REGS */ \
- { 0x00000010, 0 }, /* D4REGS */ \
- { 0x00000020, 0 }, /* D5REGS */ \
- { 0x00000040, 0 }, /* D6REGS */ \
- { 0x00000080, 0 }, /* D7REGS */ \
- { 0x000000ff, 0 }, /* DREGS */ \
- { 0x00000100, 0x000 }, /* P0REGS */ \
- { 0x00000800, 0x000 }, /* FDPIC_REGS */ \
- { 0x00000200, 0x000 }, /* FDPIC_FPTR_REGS */ \
- { 0x00004700, 0x800 }, /* PREGS_CLOBBERED */ \
- { 0x0000ff00, 0x800 }, /* PREGS */ \
- { 0x000fff00, 0x800 }, /* IPREGS */ \
- { 0x0000ffff, 0x800 }, /* DPREGS */ \
- { 0xffffffff, 0x800 }, /* MOST_REGS */\
- { 0x00000000, 0x3000 }, /* LT_REGS */\
- { 0x00000000, 0xc000 }, /* LC_REGS */\
- { 0x00000000, 0x30000 }, /* LB_REGS */\
- { 0x00000000, 0x3f7f8 }, /* PROLOGUE_REGS */\
- { 0xffffffff, 0x3fff8 }, /* NON_A_CC_REGS */\
- { 0xffffffff, 0x3ffff }} /* ALL_REGS */
-
-#define IREG_POSSIBLE_P(OUTER) \
- ((OUTER) == POST_INC || (OUTER) == PRE_INC \
- || (OUTER) == POST_DEC || (OUTER) == PRE_DEC \
- || (OUTER) == MEM || (OUTER) == ADDRESS)
-
-#define MODE_CODE_BASE_REG_CLASS(MODE, AS, OUTER, INDEX) \
+#define REG_CLASS_CONTENTS \
+ /* 31 - 0 63-32 */ \
+ { \
+ {0x00000000, 0}, /* NO_REGS */ \
+ {0x000f0000, 0}, /* IREGS */ \
+ {0x00f00000, 0}, /* BREGS */ \
+ {0x0f000000, 0}, /* LREGS */ \
+ {0xf0000000, 0}, /* MREGS */ \
+ {0x0fff0000, 0}, /* CIRCREGS */ \
+ {0xffff0000, 0}, /* DAGREGS */ \
+ {0x00000000, 0x1}, /* EVEN_AREGS */ \
+ {0x00000000, 0x2}, /* ODD_AREGS */ \
+ {0x00000000, 0x3}, /* AREGS */ \
+ {0x00000000, 0x4}, /* CCREGS */ \
+ {0x00000055, 0}, /* EVEN_DREGS */ \
+ {0x000000aa, 0}, /* ODD_DREGS */ \
+ {0x00000001, 0}, /* D0REGS */ \
+ {0x00000002, 0}, /* D1REGS */ \
+ {0x00000004, 0}, /* D2REGS */ \
+ {0x00000008, 0}, /* D3REGS */ \
+ {0x00000010, 0}, /* D4REGS */ \
+ {0x00000020, 0}, /* D5REGS */ \
+ {0x00000040, 0}, /* D6REGS */ \
+ {0x00000080, 0}, /* D7REGS */ \
+ {0x000000ff, 0}, /* DREGS */ \
+ {0x00000100, 0x000}, /* P0REGS */ \
+ {0x00000800, 0x000}, /* FDPIC_REGS */ \
+ {0x00000200, 0x000}, /* FDPIC_FPTR_REGS */ \
+ {0x00004700, 0x800}, /* PREGS_CLOBBERED */ \
+ {0x0000ff00, 0x800}, /* PREGS */ \
+ {0x000fff00, 0x800}, /* IPREGS */ \
+ {0x0000ffff, 0x800}, /* DPREGS */ \
+ {0xffffffff, 0x800}, /* MOST_REGS */ \
+ {0x00000000, 0x3000}, /* LT_REGS */ \
+ {0x00000000, 0xc000}, /* LC_REGS */ \
+ {0x00000000, 0x30000}, /* LB_REGS */ \
+ {0x00000000, 0x3f7f8}, /* PROLOGUE_REGS */ \
+ {0xffffffff, 0x3fff8}, /* NON_A_CC_REGS */ \
+ { \
+ 0xffffffff, 0x3ffff \
+ } \
+ } /* ALL_REGS */
+
+#define IREG_POSSIBLE_P(OUTER) \
+ ((OUTER) == POST_INC || (OUTER) == PRE_INC || (OUTER) == POST_DEC \
+ || (OUTER) == PRE_DEC || (OUTER) == MEM || (OUTER) == ADDRESS)
+
+#define MODE_CODE_BASE_REG_CLASS(MODE, AS, OUTER, INDEX) \
((MODE) == HImode && IREG_POSSIBLE_P (OUTER) ? IPREGS : PREGS)
-#define INDEX_REG_CLASS PREGS
+#define INDEX_REG_CLASS PREGS
-#define REGNO_OK_FOR_BASE_STRICT_P(X, MODE, OUTER, INDEX) \
- (P_REGNO_P (X) || (X) == REG_ARGP \
- || (IREG_POSSIBLE_P (OUTER) && (MODE) == HImode \
- && I_REGNO_P (X)))
+#define REGNO_OK_FOR_BASE_STRICT_P(X, MODE, OUTER, INDEX) \
+ (P_REGNO_P (X) || (X) == REG_ARGP \
+ || (IREG_POSSIBLE_P (OUTER) && (MODE) == HImode && I_REGNO_P (X)))
-#define REGNO_OK_FOR_BASE_NONSTRICT_P(X, MODE, OUTER, INDEX) \
- ((X) >= FIRST_PSEUDO_REGISTER \
+#define REGNO_OK_FOR_BASE_NONSTRICT_P(X, MODE, OUTER, INDEX) \
+ ((X) >= FIRST_PSEUDO_REGISTER \
|| REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX))
#ifdef REG_OK_STRICT
-#define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, AS, OUTER, INDEX) \
+#define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, AS, OUTER, INDEX) \
REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX)
#else
-#define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, AS, OUTER, INDEX) \
+#define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, AS, OUTER, INDEX) \
REGNO_OK_FOR_BASE_NONSTRICT_P (X, MODE, OUTER, INDEX)
#endif
-#define REGNO_OK_FOR_INDEX_P(X) 0
+#define REGNO_OK_FOR_INDEX_P(X) 0
/* The same information, inverted:
Return the class number of the smallest class containing
reg number REGNO. This could be a conditional expression
or could index an array. */
-#define REGNO_REG_CLASS(REGNO) \
-((REGNO) == REG_R0 ? D0REGS \
- : (REGNO) == REG_R1 ? D1REGS \
- : (REGNO) == REG_R2 ? D2REGS \
- : (REGNO) == REG_R3 ? D3REGS \
- : (REGNO) == REG_R4 ? D4REGS \
- : (REGNO) == REG_R5 ? D5REGS \
- : (REGNO) == REG_R6 ? D6REGS \
- : (REGNO) == REG_R7 ? D7REGS \
- : (REGNO) == REG_P0 ? P0REGS \
- : (REGNO) < REG_I0 ? PREGS \
- : (REGNO) == REG_ARGP ? PREGS \
- : (REGNO) >= REG_I0 && (REGNO) <= REG_I3 ? IREGS \
- : (REGNO) >= REG_L0 && (REGNO) <= REG_L3 ? LREGS \
- : (REGNO) >= REG_B0 && (REGNO) <= REG_B3 ? BREGS \
- : (REGNO) >= REG_M0 && (REGNO) <= REG_M3 ? MREGS \
- : (REGNO) == REG_A0 || (REGNO) == REG_A1 ? AREGS \
- : (REGNO) == REG_LT0 || (REGNO) == REG_LT1 ? LT_REGS \
- : (REGNO) == REG_LC0 || (REGNO) == REG_LC1 ? LC_REGS \
- : (REGNO) == REG_LB0 || (REGNO) == REG_LB1 ? LB_REGS \
- : (REGNO) == REG_CC ? CCREGS \
- : (REGNO) >= REG_RETS ? PROLOGUE_REGS \
- : NO_REGS)
+#define REGNO_REG_CLASS(REGNO) \
+ ((REGNO) == REG_R0 \
+ ? D0REGS \
+ : (REGNO) == REG_R1 \
+ ? D1REGS \
+ : (REGNO) == REG_R2 \
+ ? D2REGS \
+ : (REGNO) == REG_R3 \
+ ? D3REGS \
+ : (REGNO) == REG_R4 \
+ ? D4REGS \
+ : (REGNO) == REG_R5 \
+ ? D5REGS \
+ : (REGNO) == REG_R6 \
+ ? D6REGS \
+ : (REGNO) == REG_R7 \
+ ? D7REGS \
+ : (REGNO) == REG_P0 \
+ ? P0REGS \
+ : (REGNO) < REG_I0 \
+ ? PREGS \
+ : (REGNO) == REG_ARGP \
+ ? PREGS \
+ : (REGNO) >= REG_I0 \
+ && (REGNO) <= REG_I3 \
+ ? IREGS \
+ : (REGNO) >= REG_L0 \
+ && (REGNO) <= REG_L3 \
+ ? LREGS \
+ : (REGNO) >= REG_B0 \
+ && (REGNO) \
+ <= REG_B3 \
+ ? BREGS \
+ : (REGNO) >= REG_M0 \
+ && (REGNO) \
+ <= REG_M3 \
+ ? MREGS \
+ : (REGNO) \
+ == REG_A0 \
+ || (REGNO) \
+ == REG_A1 \
+ ? AREGS \
+ : (REGNO) \
+ == REG_LT0 \
+ || (REGNO) \
+ == REG_LT1 \
+ ? LT_REGS \
+ : (REGNO) \
+ == REG_LC0 \
+ || (REGNO) \
+ == REG_LC1 \
+ ? LC_REGS \
+ : (REGNO) \
+ == REG_LB0 \
+ || (REGNO) \
+ == REG_LB1 \
+ ? LB_REGS \
+ : (REGNO) \
+ == REG_CC \
+ ? CCREGS \
+ : (REGNO) \
+ >= REG_RETS \
+ ? PROLOGUE_REGS \
+ : NO_REGS)
/* When this hook returns true for MODE, the compiler allows
registers explicitly used in the rtl to be used as spill registers
@@ -668,9 +725,10 @@ enum reg_class
/* Return the maximum number of consecutive registers
needed to represent mode MODE in a register of class CLASS. */
-#define CLASS_MAX_NREGS(CLASS, MODE) \
- ((MODE) == V2PDImode && (CLASS) == AREGS ? 2 \
- : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
+#define CLASS_MAX_NREGS(CLASS, MODE) \
+ ((MODE) == V2PDImode && (CLASS) == AREGS \
+ ? 2 \
+ : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
/* A C expression that is nonzero if hard register TO can be
considered for use as a rename register for FROM register */
@@ -681,41 +739,52 @@ enum reg_class
class to use when it is necessary to copy value X into a register
in class CLASS. The value is a register class; perhaps CLASS, or
perhaps another, smaller class. */
-#define PREFERRED_RELOAD_CLASS(X, CLASS) \
- (GET_CODE (X) == POST_INC \
- || GET_CODE (X) == POST_DEC \
- || GET_CODE (X) == PRE_DEC ? PREGS : (CLASS))
+#define PREFERRED_RELOAD_CLASS(X, CLASS) \
+ (GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC \
+ || GET_CODE (X) == PRE_DEC \
+ ? PREGS \
+ : (CLASS))
/* Function Calling Conventions. */
/* The type of the current function; normal functions are of type
SUBROUTINE. */
-typedef enum {
- SUBROUTINE, INTERRUPT_HANDLER, EXCPT_HANDLER, NMI_HANDLER
+typedef enum
+{
+ SUBROUTINE,
+ INTERRUPT_HANDLER,
+ EXCPT_HANDLER,
+ NMI_HANDLER
} e_funkind;
-#define FUNCTION_RETURN_REGISTERS { REG_RETS, REG_RETI, REG_RETX, REG_RETN }
+#define FUNCTION_RETURN_REGISTERS \
+ { \
+ REG_RETS, REG_RETI, REG_RETX, REG_RETN \
+ }
-#define FUNCTION_ARG_REGISTERS { REG_R0, REG_R1, REG_R2, -1 }
+#define FUNCTION_ARG_REGISTERS \
+ { \
+ REG_R0, REG_R1, REG_R2, -1 \
+ }
/* Flags for the call/call_value rtl operations set up by function_arg */
-#define CALL_NORMAL 0x00000000 /* no special processing */
-#define CALL_LONG 0x00000001 /* always call indirect */
-#define CALL_SHORT 0x00000002 /* always call by symbol */
-
-typedef struct {
- int words; /* # words passed so far */
- int nregs; /* # registers available for passing */
- int *arg_regs; /* array of register -1 terminated */
- int call_cookie; /* Do special things for this call */
+#define CALL_NORMAL 0x00000000 /* no special processing */
+#define CALL_LONG 0x00000001 /* always call indirect */
+#define CALL_SHORT 0x00000002 /* always call by symbol */
+
+typedef struct
+{
+ int words; /* # words passed so far */
+ int nregs; /* # registers available for passing */
+ int *arg_regs; /* array of register -1 terminated */
+ int call_cookie; /* Do special things for this call */
} CUMULATIVE_ARGS;
#define FUNCTION_ARG_REGNO_P(REGNO) function_arg_regno_p (REGNO)
-
/* Initialize a variable CUM of type CUMULATIVE_ARGS
for a call to a function whose data type is FNTYPE.
For a library call, FNTYPE is 0. */
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT, N_NAMED_ARGS) \
+#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
(init_cumulative_args (&CUM, FNTYPE, LIBNAME))
/* Define how to find the value returned by a function.
@@ -726,14 +795,13 @@ typedef struct {
#define VALUE_REGNO(MODE) (REG_R0)
-#define FUNCTION_VALUE(VALTYPE, FUNC) \
- gen_rtx_REG (TYPE_MODE (VALTYPE), \
- VALUE_REGNO(TYPE_MODE(VALTYPE)))
+#define FUNCTION_VALUE(VALTYPE, FUNC) \
+ gen_rtx_REG (TYPE_MODE (VALTYPE), VALUE_REGNO (TYPE_MODE (VALTYPE)))
/* Define how to find the value returned by a library function
assuming the value has mode MODE. */
-#define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, VALUE_REGNO(MODE))
+#define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, VALUE_REGNO (MODE))
#define FUNCTION_VALUE_REGNO_P(N) ((N) == REG_R0)
@@ -750,11 +818,11 @@ typedef struct {
#define INCOMING_FRAME_SP_OFFSET 0
/* Describe how we implement __builtin_eh_return. */
-#define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
-#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, REG_P2)
-#define EH_RETURN_HANDLER_RTX \
- gen_frame_mem (Pmode, plus_constant (Pmode, frame_pointer_rtx, \
- UNITS_PER_WORD))
+#define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
+#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, REG_P2)
+#define EH_RETURN_HANDLER_RTX \
+ gen_frame_mem (Pmode, \
+ plus_constant (Pmode, frame_pointer_rtx, UNITS_PER_WORD))
/* Addressing Modes */
@@ -764,12 +832,12 @@ typedef struct {
would ever accept. */
#define MAX_REGS_PER_ADDRESS 1
-#define LEGITIMATE_MODE_FOR_AUTOINC_P(MODE) \
- (GET_MODE_SIZE (MODE) <= 4 || (MODE) == PDImode)
+#define LEGITIMATE_MODE_FOR_AUTOINC_P(MODE) \
+ (GET_MODE_SIZE (MODE) <= 4 || (MODE) == PDImode)
#define HAVE_POST_INCREMENT 1
#define HAVE_POST_DECREMENT 1
-#define HAVE_PRE_DECREMENT 1
+#define HAVE_PRE_DECREMENT 1
/* `LEGITIMATE_PIC_OPERAND_P (X)'
A C expression that is nonzero if X is a legitimate immediate
@@ -779,12 +847,11 @@ typedef struct {
not check it either. You need not define this macro if all
constants (including `SYMBOL_REF') can be immediate operands when
generating position independent code. */
-#define LEGITIMATE_PIC_OPERAND_P(X) ! SYMBOLIC_CONST (X)
+#define LEGITIMATE_PIC_OPERAND_P(X) !SYMBOLIC_CONST (X)
-#define SYMBOLIC_CONST(X) \
-(GET_CODE (X) == SYMBOL_REF \
- || GET_CODE (X) == LABEL_REF \
- || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
+#define SYMBOLIC_CONST(X) \
+ (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF \
+ || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
#define NOTICE_UPDATE_CC(EXPR, INSN) 0
@@ -811,12 +878,12 @@ typedef struct {
preferable since it may eliminate subsequent memory access if
subsequent accesses occur to other fields in the same word of the
structure, but to different bytes. */
-#define SLOW_BYTE_ACCESS 0
+#define SLOW_BYTE_ACCESS 0
#define SLOW_SHORT_ACCESS 0
/* Define this if most significant bit is lowest numbered
in instructions that operate on numbered bit-fields. */
-#define BITS_BIG_ENDIAN 0
+#define BITS_BIG_ENDIAN 0
/* Define this if most significant byte of a word is the lowest numbered.
We can't access bytes but if we could we would in the Big Endian order. */
@@ -865,12 +932,10 @@ typedef struct {
* really cause some alignment problem
*/
-#define UNITS_PER_FLOAT ((FLOAT_TYPE_SIZE + BITS_PER_UNIT - 1) / \
- BITS_PER_UNIT)
-
-#define UNITS_PER_DOUBLE ((DOUBLE_TYPE_SIZE + BITS_PER_UNIT - 1) / \
- BITS_PER_UNIT)
+#define UNITS_PER_FLOAT ((FLOAT_TYPE_SIZE + BITS_PER_UNIT - 1) / BITS_PER_UNIT)
+#define UNITS_PER_DOUBLE \
+ ((DOUBLE_TYPE_SIZE + BITS_PER_UNIT - 1) / BITS_PER_UNIT)
/* what is the 'type' of size_t */
#define SIZE_TYPE "long unsigned int"
@@ -878,11 +943,11 @@ typedef struct {
/* Define this as 1 if `char' should by default be signed; else as 0. */
#define DEFAULT_SIGNED_CHAR 1
#define FLOAT_TYPE_SIZE BITS_PER_WORD
-#define SHORT_TYPE_SIZE 16
-#define CHAR_TYPE_SIZE 8
-#define INT_TYPE_SIZE 32
-#define LONG_TYPE_SIZE 32
-#define LONG_LONG_TYPE_SIZE 64
+#define SHORT_TYPE_SIZE 16
+#define CHAR_TYPE_SIZE 8
+#define INT_TYPE_SIZE 32
+#define LONG_TYPE_SIZE 32
+#define LONG_LONG_TYPE_SIZE 64
/* Note: Fix this to depend on target switch. -- lev */
@@ -893,8 +958,8 @@ typedef struct {
* #define DOUBLES_ARE_FLOATS 1
*/
-#define DOUBLE_TYPE_SIZE 64
-#define LONG_DOUBLE_TYPE_SIZE 64
+#define DOUBLE_TYPE_SIZE 64
+#define LONG_DOUBLE_TYPE_SIZE 64
/* `PROMOTE_MODE (M, UNSIGNEDP, TYPE)'
A macro to update M and UNSIGNEDP when an object whose type is
@@ -919,18 +984,18 @@ typedef struct {
Do not define this macro if it would never modify M.*/
-#define BFIN_PROMOTE_MODE_P(MODE) \
- (!TARGET_DSP && GET_MODE_CLASS (MODE) == MODE_INT \
- && GET_MODE_SIZE (MODE) < UNITS_PER_WORD)
-
-#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
- if (BFIN_PROMOTE_MODE_P(MODE)) \
- { \
- if (MODE == QImode) \
- UNSIGNEDP = 1; \
- else if (MODE == HImode) \
- UNSIGNEDP = 0; \
- (MODE) = SImode; \
+#define BFIN_PROMOTE_MODE_P(MODE) \
+ (!TARGET_DSP && GET_MODE_CLASS (MODE) == MODE_INT \
+ && GET_MODE_SIZE (MODE) < UNITS_PER_WORD)
+
+#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
+ if (BFIN_PROMOTE_MODE_P (MODE)) \
+ { \
+ if (MODE == QImode) \
+ UNSIGNEDP = 1; \
+ else if (MODE == HImode) \
+ UNSIGNEDP = 0; \
+ (MODE) = SImode; \
}
/* Describing Relative Costs of Operations */
@@ -945,7 +1010,7 @@ typedef struct {
#define JUMP_TABLES_IN_TEXT_SECTION flag_pic
/* Define if operations between registers always perform the operation
- on the full register even if a narrower mode is specified.
+ on the full register even if a narrower mode is specified.
#define WORD_REGISTER_OPERATIONS 1
*/
@@ -953,153 +1018,183 @@ typedef struct {
together in a single multiply insn. That is the case if they are
both the same flag not involving M, or if one is a combination of
the other with M. */
-#define MACFLAGS_MATCH_P(A, B) \
- ((A) == (B) \
- || ((A) == MACFLAG_NONE && (B) == MACFLAG_M) \
- || ((A) == MACFLAG_M && (B) == MACFLAG_NONE) \
- || ((A) == MACFLAG_IS && (B) == MACFLAG_IS_M) \
- || ((A) == MACFLAG_IS_M && (B) == MACFLAG_IS))
+#define MACFLAGS_MATCH_P(A, B) \
+ ((A) == (B) || ((A) == MACFLAG_NONE && (B) == MACFLAG_M) \
+ || ((A) == MACFLAG_M && (B) == MACFLAG_NONE) \
+ || ((A) == MACFLAG_IS && (B) == MACFLAG_IS_M) \
+ || ((A) == MACFLAG_IS_M && (B) == MACFLAG_IS))
/* Switch into a generic section. */
-#define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section
+#define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section
-#define PRINT_OPERAND(FILE, RTX, CODE) print_operand (FILE, RTX, CODE)
+#define PRINT_OPERAND(FILE, RTX, CODE) print_operand (FILE, RTX, CODE)
#define PRINT_OPERAND_ADDRESS(FILE, RTX) print_address_operand (FILE, RTX)
-typedef enum sections {
- CODE_DIR,
- DATA_DIR,
- LAST_SECT_NM
+typedef enum sections
+{
+ CODE_DIR,
+ DATA_DIR,
+ LAST_SECT_NM
} SECT_ENUM_T;
-typedef enum directives {
- LONG_CONST_DIR,
- SHORT_CONST_DIR,
- BYTE_CONST_DIR,
- SPACE_DIR,
- INIT_DIR,
- LAST_DIR_NM
+typedef enum directives
+{
+ LONG_CONST_DIR,
+ SHORT_CONST_DIR,
+ BYTE_CONST_DIR,
+ SPACE_DIR,
+ INIT_DIR,
+ LAST_DIR_NM
} DIR_ENUM_T;
-#define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) \
- ((C) == ';' \
- || ((C) == '|' && (STR)[1] == '|'))
+#define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) \
+ ((C) == ';' || ((C) == '|' && (STR)[1] == '|'))
#define TEXT_SECTION_ASM_OP ".text;"
#define DATA_SECTION_ASM_OP ".data;"
-#define ASM_APP_ON ""
+#define ASM_APP_ON ""
#define ASM_APP_OFF ""
-#define ASM_GLOBALIZE_LABEL1(FILE, NAME) \
- do { fputs (".global ", FILE); \
- assemble_name (FILE, NAME); \
- fputc (';',FILE); \
- fputc ('\n',FILE); \
- } while (0)
-
-#define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \
- do { \
- fputs (".type ", FILE); \
- assemble_name (FILE, NAME); \
- fputs (", STT_FUNC", FILE); \
- fputc (';',FILE); \
- fputc ('\n',FILE); \
- ASM_OUTPUT_LABEL(FILE, NAME); \
- } while (0)
-
-#define ASM_OUTPUT_LABEL(FILE, NAME) \
- do { assemble_name (FILE, NAME); \
- fputs (":\n",FILE); \
- } while (0)
-
-#define ASM_OUTPUT_LABELREF(FILE,NAME) \
- do { fprintf (FILE, "_%s", NAME); \
- } while (0)
-
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
-do { char __buf[256]; \
- fprintf (FILE, "\t.dd\t"); \
- ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \
- assemble_name (FILE, __buf); \
- fputc (';', FILE); \
- fputc ('\n', FILE); \
- } while (0)
-
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
- MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL)
-
-#define MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
- do { \
- char __buf[256]; \
- fprintf (FILE, "\t.dd\t"); \
- ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \
- assemble_name (FILE, __buf); \
- fputs (" - ", FILE); \
- ASM_GENERATE_INTERNAL_LABEL (__buf, "L", REL); \
- assemble_name (FILE, __buf); \
- fputc (';', FILE); \
- fputc ('\n', FILE); \
- } while (0)
-
-#define ASM_OUTPUT_ALIGN(FILE,LOG) \
- do { \
- if ((LOG) != 0) \
- fprintf (FILE, "\t.align %d\n", 1 << (LOG)); \
- } while (0)
-
-#define ASM_OUTPUT_SKIP(FILE,SIZE) \
- do { \
- asm_output_skip (FILE, SIZE); \
- } while (0)
-
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
-do { \
- switch_to_section (data_section); \
- if ((SIZE) >= (unsigned int) 4 ) ASM_OUTPUT_ALIGN(FILE,2); \
- ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, SIZE); \
- ASM_OUTPUT_LABEL (FILE, NAME); \
- fprintf (FILE, "%s %ld;\n", ASM_SPACE, \
- (ROUNDED) > (unsigned int) 1 ? (ROUNDED) : 1); \
-} while (0)
-
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
- do { \
- ASM_GLOBALIZE_LABEL1(FILE,NAME); \
- ASM_OUTPUT_LOCAL (FILE, NAME, SIZE, ROUNDED); } while(0)
+#define ASM_GLOBALIZE_LABEL1(FILE, NAME) \
+ do \
+ { \
+ fputs (".global ", FILE); \
+ assemble_name (FILE, NAME); \
+ fputc (';', FILE); \
+ fputc ('\n', FILE); \
+ } \
+ while (0)
+
+#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
+ do \
+ { \
+ fputs (".type ", FILE); \
+ assemble_name (FILE, NAME); \
+ fputs (", STT_FUNC", FILE); \
+ fputc (';', FILE); \
+ fputc ('\n', FILE); \
+ ASM_OUTPUT_LABEL (FILE, NAME); \
+ } \
+ while (0)
+
+#define ASM_OUTPUT_LABEL(FILE, NAME) \
+ do \
+ { \
+ assemble_name (FILE, NAME); \
+ fputs (":\n", FILE); \
+ } \
+ while (0)
+
+#define ASM_OUTPUT_LABELREF(FILE, NAME) \
+ do \
+ { \
+ fprintf (FILE, "_%s", NAME); \
+ } \
+ while (0)
+
+#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
+ do \
+ { \
+ char __buf[256]; \
+ fprintf (FILE, "\t.dd\t"); \
+ ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \
+ assemble_name (FILE, __buf); \
+ fputc (';', FILE); \
+ fputc ('\n', FILE); \
+ } \
+ while (0)
+
+#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
+ MY_ASM_OUTPUT_ADDR_DIFF_ELT (FILE, VALUE, REL)
+
+#define MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
+ do \
+ { \
+ char __buf[256]; \
+ fprintf (FILE, "\t.dd\t"); \
+ ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \
+ assemble_name (FILE, __buf); \
+ fputs (" - ", FILE); \
+ ASM_GENERATE_INTERNAL_LABEL (__buf, "L", REL); \
+ assemble_name (FILE, __buf); \
+ fputc (';', FILE); \
+ fputc ('\n', FILE); \
+ } \
+ while (0)
+
+#define ASM_OUTPUT_ALIGN(FILE, LOG) \
+ do \
+ { \
+ if ((LOG) != 0) \
+ fprintf (FILE, "\t.align %d\n", 1 << (LOG)); \
+ } \
+ while (0)
+
+#define ASM_OUTPUT_SKIP(FILE, SIZE) \
+ do \
+ { \
+ asm_output_skip (FILE, SIZE); \
+ } \
+ while (0)
+
+#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
+ do \
+ { \
+ switch_to_section (data_section); \
+ if ((SIZE) >= (unsigned int) 4) \
+ ASM_OUTPUT_ALIGN (FILE, 2); \
+ ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, SIZE); \
+ ASM_OUTPUT_LABEL (FILE, NAME); \
+ fprintf (FILE, "%s %ld;\n", ASM_SPACE, \
+ (ROUNDED) > (unsigned int) 1 ? (ROUNDED) : 1); \
+ } \
+ while (0)
+
+#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
+ do \
+ { \
+ ASM_GLOBALIZE_LABEL1 (FILE, NAME); \
+ ASM_OUTPUT_LOCAL (FILE, NAME, SIZE, ROUNDED); \
+ } \
+ while (0)
#define ASM_COMMENT_START "//"
#define PROFILE_BEFORE_PROLOGUE
-#define FUNCTION_PROFILER(FILE, LABELNO) \
- do { \
- fprintf (FILE, "\t[--SP] = RETS;\n"); \
- if (TARGET_LONG_CALLS) \
- { \
- fprintf (FILE, "\tP2.h = __mcount;\n"); \
- fprintf (FILE, "\tP2.l = __mcount;\n"); \
- fprintf (FILE, "\tCALL (P2);\n"); \
- } \
- else \
- fprintf (FILE, "\tCALL __mcount;\n"); \
- fprintf (FILE, "\tRETS = [SP++];\n"); \
- } while(0)
+#define FUNCTION_PROFILER(FILE, LABELNO) \
+ do \
+ { \
+ fprintf (FILE, "\t[--SP] = RETS;\n"); \
+ if (TARGET_LONG_CALLS) \
+ { \
+ fprintf (FILE, "\tP2.h = __mcount;\n"); \
+ fprintf (FILE, "\tP2.l = __mcount;\n"); \
+ fprintf (FILE, "\tCALL (P2);\n"); \
+ } \
+ else \
+ fprintf (FILE, "\tCALL __mcount;\n"); \
+ fprintf (FILE, "\tRETS = [SP++];\n"); \
+ } \
+ while (0)
#undef NO_PROFILE_COUNTERS
#define NO_PROFILE_COUNTERS 1
-#define ASM_OUTPUT_REG_PUSH(FILE, REGNO) fprintf (FILE, "\t[--SP] = %s;\n", reg_names[REGNO])
-#define ASM_OUTPUT_REG_POP(FILE, REGNO) fprintf (FILE, "\t%s = [SP++];\n", reg_names[REGNO])
+#define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
+ fprintf (FILE, "\t[--SP] = %s;\n", reg_names[REGNO])
+#define ASM_OUTPUT_REG_POP(FILE, REGNO) \
+ fprintf (FILE, "\t%s = [SP++];\n", reg_names[REGNO])
extern rtx bfin_cc_rtx, bfin_rets_rtx;
/* This works for GAS and some other assemblers. */
-#define SET_ASM_OP ".set "
+#define SET_ASM_OP ".set "
/* DBX register number for a given compiler register number */
-#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
+#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
-#define SIZE_ASM_OP "\t.size\t"
+#define SIZE_ASM_OP "\t.size\t"
extern int splitting_for_sched, splitting_loops;
diff --git a/gcc/config/c6x/c6x-rust.c b/gcc/config/c6x/c6x-rust.c
index 351adac..57812b0 100644
--- a/gcc/config/c6x/c6x-rust.c
+++ b/gcc/config/c6x/c6x-rust.c
@@ -29,7 +29,6 @@ void c6x_rust_target_cpu_info(void) {
rust_add_target_info("target_arch", "tic6x");
// llvm seems to have no support for c6x (nor historical support), so names are made up by me
- // TODO: very subject to change
// TODO maybe put in sub-arches as features? idk
if (TARGET_DSBT)
rust_add_target_info("target_feature", "dsbt");
diff --git a/gcc/config/cr16/cr16-rust.c b/gcc/config/cr16/cr16-rust.c
index 3b9efe3..b6c7a76 100644
--- a/gcc/config/cr16/cr16-rust.c
+++ b/gcc/config/cr16/cr16-rust.c
@@ -29,7 +29,6 @@ void cr16_rust_target_cpu_info(void) {
rust_add_target_info("target_arch", "cr16");
// llvm seems to have no support for cr16 (nor historical support), so names are made up by me
- // TODO: very subject to change
// TODO maybe put in sub-arches as features? idk
if (TARGET_BIT_OPS)
rust_add_target_info("target_feature", "bit-ops");
diff --git a/gcc/config/csky/csky-rust.c b/gcc/config/csky/csky-rust.c
index 16dd7b2..44c34cd 100644
--- a/gcc/config/csky/csky-rust.c
+++ b/gcc/config/csky/csky-rust.c
@@ -29,7 +29,6 @@ void cris_rust_target_cpu_info(void) {
rust_add_target_info("target_arch", "csky");
// llvm seems to have no support for sky (nor historical support), so names are made up by me
- // TODO: very subject to change
// TODO maybe put in sub-arches as features? idk. might be useful in this case
if (TARGET_HARD_FLOAT)
rust_add_target_info("target_feature", "hard-float");
diff --git a/gcc/config/epiphany/epiphany-rust.c b/gcc/config/epiphany/epiphany-rust.c
index 19df9ce..952f867 100644
--- a/gcc/config/epiphany/epiphany-rust.c
+++ b/gcc/config/epiphany/epiphany-rust.c
@@ -29,7 +29,6 @@ void epiphany_rust_target_cpu_info(void) {
rust_add_target_info("target_arch", "epiphany");
// llvm seems to have no support for sky (nor historical support), so names are made up by me
- // TODO: very subject to change
// TODO: should the "no" dichotomy be preserved? probably not, but which should be chosen?
if (TARGET_HALF_REG_FILE)
rust_add_target_info("target_feature", "half-reg-file");
diff --git a/gcc/config/frv/frv-rust.c b/gcc/config/frv/frv-rust.c
index 3dc7dc8..ed66a12 100644
--- a/gcc/config/frv/frv-rust.c
+++ b/gcc/config/frv/frv-rust.c
@@ -29,7 +29,6 @@ void frv_rust_target_cpu_info(void) {
rust_add_target_info("target_arch", "frv");
// llvm seems to have no support for sky (nor historical support), so names are made up by me
- // TODO: very subject to change
// TODO maybe put in sub-arches as features? idk. might be useful in this case
if (TARGET_ACC_4)
rust_add_target_info("target_feature", "acc-4");
diff --git a/gcc/config/ft32/ft32.h b/gcc/config/ft32/ft32.h
index eb63c5b..769f3b3 100644
--- a/gcc/config/ft32/ft32.h
+++ b/gcc/config/ft32/ft32.h
@@ -468,7 +468,8 @@ do { \
rust_add_target_info("target_arch", "ft32"); \
if (TARGET_SIM) \
rust_add_target_info("target_feature", "sim"); \
- /*TODO: figure out how to use lra option*/ \
+ if (ft32_lra_flag) \
+ rust_add_target_info("target_feature", "lra"); \
if (TARGET_NODIV) \
rust_add_target_info("target_feature", "nodiv"); \
if (TARGET_FT32B) \
diff --git a/gcc/config/ia64/ia64-rust.c b/gcc/config/ia64/ia64-rust.c
index 0dac53d..f21cf48 100644
--- a/gcc/config/ia64/ia64-rust.c
+++ b/gcc/config/ia64/ia64-rust.c
@@ -95,8 +95,6 @@ void ia64_rust_target_cpu_info(void) {
rust_add_target_info("target_feature", "early-stop-bits");
// TODO: do fixed-range somehow (wouldn't work well as define, I don't think), same for tls-size
- /* TODO: ensure that these variables below are actually accessible, and work (i.e. condition test not
- * wrong way around). */
if (mflag_sched_br_data_spec)
rust_add_target_info("target_feature", "sched-br-data-spec");
if (mflag_sched_ar_data_spec)
generated by cgit v1.1 at 2025-05-22 04:06:03 +0000