m68k.md: Switch from the "*..." syntax to the brace-enclosed syntax in all C output...

	* gcc/config/m68k/m68k.md: Switch from the "*..." syntax to the
	brace-enclosed syntax in all C output statements.

From-SVN: r75705

2 files changed, 967 insertions, 1146 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index b08d87c..0f76db1 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2004-01-12  Bernardo Innocenti  <bernie@develer.com>
+
+	* gcc/config/m68k/m68k.md: Switch from the "*..." syntax to the
+	brace-enclosed syntax in all C output statements.
+
 2004-01-12  David Edelsohn  <edelsohn@gnu.org>
 
 	PR target/13401
diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md
index 11f219c..f3550f3 100644
--- a/gcc/config/m68k/m68k.md
+++ b/gcc/config/m68k/m68k.md
@@ -127,21 +127,19 @@
   [(set (match_operand:DF 0 "push_operand" "=m")
 	(match_operand:DF 1 "general_operand" "ro<>fyE"))]
   ""
-  "*
 {
   if (FP_REG_P (operands[1]))
-    return \"fmove%.d %f1,%0\";
+    return "fmove%.d %f1,%0";
   return output_move_double (operands);
-}")
+})
 
 (define_insn "pushdi"
   [(set (match_operand:DI 0 "push_operand" "=m")
 	(match_operand:DI 1 "general_operand" "ro<>Fyi"))]
   ""
-  "*
 {
   return output_move_double (operands);
-}")
+})
 
 ;; We don't want to allow a constant operand for test insns because
 ;; (set (cc0) (const_int foo)) has no mode information.  Such insns will
@@ -161,7 +159,6 @@
    (clobber (match_scratch:SI 1 "=X,d"))
    (clobber (match_scratch:DI 2 "=d,X"))]
   ""
-  "*
 {
   if (which_alternative == 0)
     {
@@ -171,21 +168,21 @@
       xoperands[1] = operands[0];
       output_move_double (xoperands);
       cc_status.flags |= CC_REVERSED;
-      return \"neg%.l %R2\;negx%.l %2\";
+      return "neg%.l %R2\;negx%.l %2";
     }
   if (find_reg_note (insn, REG_DEAD, operands[0]))
     {
       cc_status.flags |= CC_REVERSED;
-      return \"neg%.l %R0\;negx%.l %0\";
+      return "neg%.l %R0\;negx%.l %0";
     }
   else
     /*
-    ** 'sub' clears %1, and also clears the X cc bit
-    ** 'tst' sets the Z cc bit according to the low part of the DImode operand
-    ** 'subx %1' (i.e. subx #0) acts as a (non-existent) tstx on the high part
+       'sub' clears %1, and also clears the X cc bit
+       'tst' sets the Z cc bit according to the low part of the DImode operand
+       'subx %1' (i.e. subx #0) acts as a (non-existent) tstx on the high part.
     */
-    return \"sub%.l %1,%1\;tst%.l %R0\;subx%.l %1,%0\";
-}")
+    return "sub%.l %1,%1\;tst%.l %R0\;subx%.l %1,%0";
+})
 
 (define_expand "tstsi"
   [(set (cc0)
@@ -197,19 +194,18 @@
   [(set (cc0)
 	(match_operand:SI 0 "nonimmediate_operand" "rm"))]
   ""
-  "*
 {
   if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0]))
-    return \"tst%.l %0\";
+    return "tst%.l %0";
   /* If you think that the 68020 does not support tstl a0,
      reread page B-167 of the 68020 manual more carefully.  */
   /* On an address reg, cmpw may replace cmpl.  */
 #ifdef SGS_CMP_ORDER
-  return \"cmp%.w %0,%#0\";
+  return "cmp%.w %0,%#0";
 #else
-  return \"cmp%.w %#0,%0\";
+  return "cmp%.w %#0,%0";
 #endif
-}")
+})
 
 ;; This can't use an address register, because comparisons
 ;; with address registers as second operand always test the whole word.
@@ -250,13 +246,12 @@
   [(set (cc0)
 	(match_operand:SF 0 "general_operand" "fdm"))]
   "TARGET_68881"
-  "*
 {
   cc_status.flags = CC_IN_68881;
   if (FP_REG_P (operands[0]))
-    return \"ftst%.x %0\";
-  return \"ftst%.s %0\";
-}")
+    return "ftst%.x %0";
+  return "ftst%.s %0";
+})
 
 (define_expand "tstdf"
   [(set (cc0)
@@ -271,13 +266,12 @@
   [(set (cc0)
 	(match_operand:DF 0 "general_operand" "fm"))]
   "TARGET_68881"
-  "*
 {
   cc_status.flags = CC_IN_68881;
   if (FP_REG_P (operands[0]))
-    return \"ftst%.x %0\";
-  return \"ftst%.d %0\";
-}")
+    return "ftst%.x %0";
+  return "ftst%.d %0";
+})
 
 ;; compare instructions.
 
@@ -296,16 +290,15 @@
 		 (match_operand:DI 2 "general_operand" "d,0")))
    (clobber (match_operand:DI 0 "register_operand" "=d,d"))]
   ""
-  "*
 {
   if (rtx_equal_p (operands[0], operands[1]))
-    return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
+    return "sub%.l %R2,%R0\;subx%.l %2,%0";
   else
     {
       cc_status.flags |= CC_REVERSED;
-      return \"sub%.l %R1,%R0\;subx%.l %1,%0\";
+      return "sub%.l %R1,%R0\;subx%.l %1,%0";
     }
-}")
+})
 
 ;; This is the second "hook" for PIC code (in addition to movsi). See
 ;; comment of movsi for a description of PIC handling.
@@ -334,21 +327,20 @@
         (compare (match_operand:SI 0 "nonimmediate_operand" "rKT,rKs,mSr,mSa,>")
                  (match_operand:SI 1 "general_src_operand" "mSr,mSa,KTr,Ksr,>")))]
   "!TARGET_COLDFIRE"
-  "*
 {
   if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
 #ifdef SGS_CMP_ORDER
-    return \"cmpm%.l %0,%1\";
+    return "cmpm%.l %0,%1";
 #else
-    return \"cmpm%.l %1,%0\";
+    return "cmpm%.l %1,%0";
 #endif
   if (REG_P (operands[1])
       || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
     { cc_status.flags |= CC_REVERSED;
 #ifdef SGS_CMP_ORDER
-      return \"cmp%.l %d1,%d0\";
+      return "cmp%.l %d1,%d0";
 #else
-      return \"cmp%.l %d0,%d1\";
+      return "cmp%.l %d0,%d1";
 #endif
     }
   if (ADDRESS_REG_P (operands[0])
@@ -357,40 +349,39 @@
       && INTVAL (operands[1]) >= -0x8000)
     {
 #ifdef SGS_CMP_ORDER
-      return \"cmp%.w %0,%1\";
+      return "cmp%.w %0,%1";
 #else
-      return \"cmp%.w %1,%0\";
+      return "cmp%.w %1,%0";
 #endif
     }
 #ifdef SGS_CMP_ORDER
-  return \"cmp%.l %d0,%d1\";
+  return "cmp%.l %d0,%d1";
 #else
-  return \"cmp%.l %d1,%d0\";
+  return "cmp%.l %d1,%d0";
 #endif
-}")
+})
 
 (define_insn ""
   [(set (cc0)
 	(compare (match_operand:SI 0 "nonimmediate_operand" "mrKs,r")
 		 (match_operand:SI 1 "general_operand" "r,mrKs")))]
   "TARGET_COLDFIRE"
-  "*
 {
   if (REG_P (operands[1])
       || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
     { cc_status.flags |= CC_REVERSED;
 #ifdef SGS_CMP_ORDER
-      return \"cmp%.l %d1,%d0\";
+      return "cmp%.l %d1,%d0";
 #else
-      return \"cmp%.l %d0,%d1\";
+      return "cmp%.l %d0,%d1";
 #endif
     }
 #ifdef SGS_CMP_ORDER
-  return \"cmp%.l %d0,%d1\";
+  return "cmp%.l %d0,%d1";
 #else
-  return \"cmp%.l %d1,%d0\";
+  return "cmp%.l %d1,%d0";
 #endif
-}")
+})
 
 (define_expand "cmphi"
   [(set (cc0)
@@ -404,29 +395,28 @@
         (compare (match_operand:HI 0 "nonimmediate_src_operand" "rnmS,d,n,mS,>")
                  (match_operand:HI 1 "general_src_operand" "d,rnmS,mS,n,>")))]
   "!TARGET_COLDFIRE"
-  "*
 {
   if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
 #ifdef SGS_CMP_ORDER
-    return \"cmpm%.w %0,%1\";
+    return "cmpm%.w %0,%1";
 #else
-    return \"cmpm%.w %1,%0\";
+    return "cmpm%.w %1,%0";
 #endif
   if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1]))
       || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
     { cc_status.flags |= CC_REVERSED;
 #ifdef SGS_CMP_ORDER
-      return \"cmp%.w %d1,%d0\";
+      return "cmp%.w %d1,%d0";
 #else
-      return \"cmp%.w %d0,%d1\";
+      return "cmp%.w %d0,%d1";
 #endif
     }
 #ifdef SGS_CMP_ORDER
-  return \"cmp%.w %d0,%d1\";
+  return "cmp%.w %d0,%d1";
 #else
-  return \"cmp%.w %d1,%d0\";
+  return "cmp%.w %d1,%d0";
 #endif
-}")
+})
 
 (define_expand "cmpqi"
   [(set (cc0)
@@ -440,29 +430,28 @@
         (compare (match_operand:QI 0 "nonimmediate_src_operand" "dn,dmS,>")
                  (match_operand:QI 1 "general_src_operand" "dmS,nd,>")))]
   "!TARGET_COLDFIRE"
-  "*
 {
   if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
 #ifdef SGS_CMP_ORDER
-    return \"cmpm%.b %0,%1\";
+    return "cmpm%.b %0,%1";
 #else
-    return \"cmpm%.b %1,%0\";
+    return "cmpm%.b %1,%0";
 #endif
   if (REG_P (operands[1])
       || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
     { cc_status.flags |= CC_REVERSED;
 #ifdef SGS_CMP_ORDER
-      return \"cmp%.b %d1,%d0\";
+      return "cmp%.b %d1,%d0";
 #else
-      return \"cmp%.b %d0,%d1\";
+      return "cmp%.b %d0,%d1";
 #endif
     }
 #ifdef SGS_CMP_ORDER
-  return \"cmp%.b %d0,%d1\";
+  return "cmp%.b %d0,%d1";
 #else
-  return \"cmp%.b %d1,%d0\";
+  return "cmp%.b %d1,%d0";
 #endif
-}")
+})
 
 (define_expand "cmpdf"
   [(set (cc0)
@@ -479,31 +468,30 @@
 	(compare (match_operand:DF 0 "general_operand" "f,mG")
 		 (match_operand:DF 1 "general_operand" "fmG,f")))]
   "TARGET_68881"
-  "*
 {
   cc_status.flags = CC_IN_68881;
 #ifdef SGS_CMP_ORDER
   if (REG_P (operands[0]))
     {
       if (REG_P (operands[1]))
-	return \"fcmp%.x %0,%1\";
+	return "fcmp%.x %0,%1";
       else
-        return \"fcmp%.d %0,%f1\";
+        return "fcmp%.d %0,%f1";
     }
   cc_status.flags |= CC_REVERSED;
-  return \"fcmp%.d %1,%f0\";
+  return "fcmp%.d %1,%f0";
 #else
   if (REG_P (operands[0]))
     {
       if (REG_P (operands[1]))
-	return \"fcmp%.x %1,%0\";
+	return "fcmp%.x %1,%0";
       else
-        return \"fcmp%.d %f1,%0\";
+        return "fcmp%.d %f1,%0";
     }
   cc_status.flags |= CC_REVERSED;
-  return \"fcmp%.d %f0,%1\";
+  return "fcmp%.d %f0,%1";
 #endif
-}")
+})
 
 (define_expand "cmpsf"
  [(set (cc0)
@@ -520,31 +508,30 @@
 	(compare (match_operand:SF 0 "general_operand" "f,mdG")
 		 (match_operand:SF 1 "general_operand" "fmdG,f")))]
   "TARGET_68881"
-  "*
 {
   cc_status.flags = CC_IN_68881;
 #ifdef SGS_CMP_ORDER
   if (FP_REG_P (operands[0]))
     {
       if (FP_REG_P (operands[1]))
-	return \"fcmp%.x %0,%1\";
+	return "fcmp%.x %0,%1";
       else
-        return \"fcmp%.s %0,%f1\";
+        return "fcmp%.s %0,%f1";
     }
   cc_status.flags |= CC_REVERSED;
-  return \"fcmp%.s %1,%f0\";
+  return "fcmp%.s %1,%f0";
 #else
   if (FP_REG_P (operands[0]))
     {
       if (FP_REG_P (operands[1]))
-	return \"fcmp%.x %1,%0\";
+	return "fcmp%.x %1,%0";
       else
-        return \"fcmp%.s %f1,%0\";
+        return "fcmp%.s %f1,%0";
     }
   cc_status.flags |= CC_REVERSED;
-  return \"fcmp%.s %f0,%1\";
+  return "fcmp%.s %f0,%1";
 #endif
-}")
+})
 
 ;; Recognizers for btst instructions.
 
@@ -558,7 +545,9 @@
 			    (minus:SI (const_int 7)
 				      (match_operand:SI 1 "general_operand" "di"))))]
   "!TARGET_COLDFIRE"
-  "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
+{
+  return output_btst (operands, operands[1], operands[0], insn, 7);
+})
 
 ;; This is the same as the above pattern except for the constraints.  The 'i'
 ;; has been deleted.
@@ -569,7 +558,9 @@
 			    (minus:SI (const_int 7)
 				      (match_operand:SI 1 "general_operand" "d"))))]
   "TARGET_COLDFIRE"
-  "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
+{
+  return output_btst (operands, operands[1], operands[0], insn, 7);
+})
 
 (define_insn ""
   [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
@@ -577,7 +568,9 @@
 			    (minus:SI (const_int 31)
 				      (match_operand:SI 1 "general_operand" "di"))))]
   ""
-  "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
+{
+  return output_btst (operands, operands[1], operands[0], insn, 31);
+})
 
 ;; The following two patterns are like the previous two
 ;; except that they use the fact that bit-number operands
@@ -591,7 +584,9 @@
 				       (match_operand:SI 1 "register_operand" "d")
 				       (const_int 7)))))]
   ""
-  "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
+{
+  return output_btst (operands, operands[1], operands[0], insn, 7);
+})
 
 (define_insn ""
   [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
@@ -601,7 +596,9 @@
 				       (match_operand:SI 1 "register_operand" "d")
 				       (const_int 31)))))]
   ""
-  "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
+{
+  return output_btst (operands, operands[1], operands[0], insn, 31);
+})
 
 ;; Nonoffsettable mem refs are ok in this one pattern
 ;; since we don't try to adjust them.
@@ -610,18 +607,16 @@
 			    (const_int 1)
 			    (match_operand:SI 1 "const_int_operand" "n")))]
   "(unsigned) INTVAL (operands[1]) < 8 && !TARGET_COLDFIRE"
-  "*
 {
   operands[1] = GEN_INT (7 - INTVAL (operands[1]));
   return output_btst (operands, operands[1], operands[0], insn, 7);
-}")
+})
 
 (define_insn ""
   [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "do")
 			    (const_int 1)
 			    (match_operand:SI 1 "const_int_operand" "n")))]
   "!TARGET_COLDFIRE"
-  "*
 {
   if (GET_CODE (operands[0]) == MEM)
     {
@@ -632,7 +627,7 @@
     }
   operands[1] = GEN_INT (31 - INTVAL (operands[1]));
   return output_btst (operands, operands[1], operands[0], insn, 31);
-}")
+})
 
 ;; This is the same as the above pattern except for the constraints.
 ;; The 'o' has been replaced with 'Q'.
@@ -642,7 +637,6 @@
 			    (const_int 1)
 			    (match_operand:SI 1 "const_int_operand" "n")))]
   "TARGET_COLDFIRE"
-  "*
 {
   if (GET_CODE (operands[0]) == MEM)
     {
@@ -653,7 +647,7 @@
     }
   operands[1] = GEN_INT (31 - INTVAL (operands[1]));
   return output_btst (operands, operands[1], operands[0], insn, 31);
-}")
+})
 
 
 ;; move instructions
@@ -664,12 +658,11 @@
   [(set (match_operand:SI 0 "push_operand" "=m")
 	(match_operand:SI 1 "const_int_operand" "J"))]
   "INTVAL (operands[1]) >= -0x8000 && INTVAL (operands[1]) < 0x8000"
-  "*
 {
   if (operands[1] == const0_rtx)
-    return \"clr%.l %0\";
-  return \"pea %a1\";
-}")
+    return "clr%.l %0";
+  return "pea %a1";
+})
 
 ;This is never used.
 ;(define_insn "swapsi"
@@ -690,28 +683,27 @@
   ;; This isn't so on the 68010, but we have no TARGET_68010.
   "((TARGET_68020 || TARGET_COLDFIRE)
     || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))"
-  "*
 {
   if (ADDRESS_REG_P (operands[0]))
     {
       /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
       if (!TARGET_68040 && !TARGET_68060)
-	return \"sub%.l %0,%0\";
+	return "sub%.l %0,%0";
       else
 	return MOTOROLA ?
 #ifdef SGS
 	  /* Many SGS assemblers croak on size specifiers for constants.  */
-	  \"lea 0,%0\" :
+	  "lea 0,%0" :
 #else
-	  \"lea 0.w,%0\" :
+	  "lea 0.w,%0" :
 #endif
-	  \"lea 0:w,%0\";
+	  "lea 0:w,%0";
     }
   /* moveq is faster on the 68000.  */
   if (DATA_REG_P (operands[0]) && (!TARGET_68020 && !TARGET_COLDFIRE))
-    return \"moveq %#0,%0\";
-  return \"clr%.l %0\";
-}")
+    return "moveq %#0,%0";
+  return "clr%.l %0";
+})
 
 ;; General case of fullword move.
 ;;
@@ -760,10 +752,9 @@
         (match_operand:SI 1 "general_src_operand" "daymSKT,n,i"))]
 
   "!TARGET_COLDFIRE"
-  "*
 {
   return output_move_simode (operands);
-}")
+})
 
 (define_insn ""
   [(set (match_operand:SI 0 "nonimmediate_operand" "=r<Q>,g")
@@ -777,12 +768,11 @@
   [(set (match_operand:SI 0 "nonimmediate_operand" "=a<")
         (match_operand:SI 1 "pcrel_address" ""))]
   "TARGET_PCREL"
-  "*
 {
   if (push_operand (operands[0], SImode))
-    return \"pea %a1\";
-  return \"lea %a1,%0\";
-}")
+    return "pea %a1";
+  return "lea %a1,%0";
+})
 
 (define_expand "movhi"
   [(set (match_operand:HI 0 "nonimmediate_operand" "")
@@ -873,23 +863,22 @@
   [(set (match_operand:SF 0 "nonimmediate_operand" "=rmf")
 	(match_operand:SF 1 "general_operand" "rmfF"))]
   "!TARGET_COLDFIRE"
-  "*
 {
   if (FP_REG_P (operands[0]))
     {
       if (FP_REG_P (operands[1]))
-	return \"f%$move%.x %1,%0\";
+	return "f%$move%.x %1,%0";
       else if (ADDRESS_REG_P (operands[1]))
-	return \"move%.l %1,%-\;f%$move%.s %+,%0\";
+	return "move%.l %1,%-\;f%$move%.s %+,%0";
       else if (GET_CODE (operands[1]) == CONST_DOUBLE)
 	return output_move_const_single (operands);
-      return \"f%$move%.s %f1,%0\";
+      return "f%$move%.s %f1,%0";
     }
   if (FP_REG_P (operands[1]))
     {
       if (ADDRESS_REG_P (operands[0]))
-	return \"fmove%.s %1,%-\;move%.l %+,%0\";
-      return \"fmove%.s %f1,%0\";
+	return "fmove%.s %1,%-\;move%.l %+,%0";
+      return "fmove%.s %f1,%0";
     }
   if (operands[1] == CONST0_RTX (SFmode)
       /* clr insns on 68000 read before writing.
@@ -901,32 +890,34 @@
 	{
 	  /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
 	  if (!TARGET_68040 && !TARGET_68060)
-	    return \"sub%.l %0,%0\";
+	    return "sub%.l %0,%0";
 	  else
 	    return MOTOROLA ?
 #ifdef SGS
 	      /* Many SGS assemblers croak on size specifiers for constants.  */
-	      \"lea 0,%0\" :
+	      "lea 0,%0" :
 #else
-	      \"lea 0.w,%0\" :
+	      "lea 0.w,%0" :
 #endif
-	      \"lea 0:w,%0\";
+	      "lea 0:w,%0";
 	}
       /* moveq is faster on the 68000.  */
       if (DATA_REG_P (operands[0]) && !(TARGET_68020 || TARGET_COLDFIRE))
 	{
-	  return \"moveq %#0,%0\";
+	  return "moveq %#0,%0";
 	}
-      return \"clr%.l %0\";
+      return "clr%.l %0";
     }
-  return \"move%.l %1,%0\";
-}")
+  return "move%.l %1,%0";
+})
 
 (define_insn ""
   [(set (match_operand:SF 0 "nonimmediate_operand" "=r,g")
 	(match_operand:SF 1 "general_operand" "g,r"))]
   "TARGET_COLDFIRE"
-  "* return \"move%.l %1,%0\";")
+{
+  return "move%.l %1,%0";
+})
 
 (define_expand "movdf"
   [(set (match_operand:DF 0 "nonimmediate_operand" "")
@@ -940,43 +931,44 @@
 ;  [(set (match_operand:DF 0 "nonimmediate_operand" "=rm,&rf,&rof<>")
 ;	(match_operand:DF 1 "general_operand" "rf,m,rofF<>"))]
   "!TARGET_COLDFIRE"
-  "*
 {
   if (FP_REG_P (operands[0]))
     {
       if (FP_REG_P (operands[1]))
-	return \"f%&move%.x %1,%0\";
+	return "f%&move%.x %1,%0";
       if (REG_P (operands[1]))
 	{
 	  rtx xoperands[2];
 	  xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
-	  output_asm_insn (\"move%.l %1,%-\", xoperands);
-	  output_asm_insn (\"move%.l %1,%-\", operands);
-	  return \"f%&move%.d %+,%0\";
+	  output_asm_insn ("move%.l %1,%-", xoperands);
+	  output_asm_insn ("move%.l %1,%-", operands);
+	  return "f%&move%.d %+,%0";
 	}
       if (GET_CODE (operands[1]) == CONST_DOUBLE)
 	return output_move_const_double (operands);
-      return \"f%&move%.d %f1,%0\";
+      return "f%&move%.d %f1,%0";
     }
   else if (FP_REG_P (operands[1]))
     {
       if (REG_P (operands[0]))
 	{
-	  output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
+	  output_asm_insn ("fmove%.d %f1,%-\;move%.l %+,%0", operands);
 	  operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-	  return \"move%.l %+,%0\";
+	  return "move%.l %+,%0";
 	}
       else
-        return \"fmove%.d %f1,%0\";
+        return "fmove%.d %f1,%0";
     }
   return output_move_double (operands);
-}")
+})
 
 (define_insn ""
   [(set (match_operand:DF 0 "nonimmediate_operand" "=r,g")
 	(match_operand:DF 1 "general_operand" "g,r"))]
   "TARGET_COLDFIRE"
-  "* return output_move_double (operands);")
+{
+  return output_move_double (operands);
+})
 
 ;; ??? The XFmode patterns are schizophrenic about whether constants are
 ;; allowed.  Most but not all have predicates and constraint that disallow
@@ -1014,83 +1006,79 @@
   [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,!r,!f,!r")
 	(match_operand:XF 1 "nonimmediate_operand" "m,f,f,f,r,!r"))]
   "TARGET_68881"
-  "*
 {
   if (FP_REG_P (operands[0]))
     {
       if (FP_REG_P (operands[1]))
-	return \"fmove%.x %1,%0\";
+	return "fmove%.x %1,%0";
       if (REG_P (operands[1]))
 	{
 	  rtx xoperands[2];
 	  xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
-	  output_asm_insn (\"move%.l %1,%-\", xoperands);
+	  output_asm_insn ("move%.l %1,%-", xoperands);
 	  xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
-	  output_asm_insn (\"move%.l %1,%-\", xoperands);
-	  output_asm_insn (\"move%.l %1,%-\", operands);
-	  return \"fmove%.x %+,%0\";
+	  output_asm_insn ("move%.l %1,%-", xoperands);
+	  output_asm_insn ("move%.l %1,%-", operands);
+	  return "fmove%.x %+,%0";
 	}
       if (GET_CODE (operands[1]) == CONST_DOUBLE)
-        return \"fmove%.x %1,%0\";
-      return \"fmove%.x %f1,%0\";
+        return "fmove%.x %1,%0";
+      return "fmove%.x %f1,%0";
     }
   if (FP_REG_P (operands[1]))
     {
       if (REG_P (operands[0]))
 	{
-	  output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
+	  output_asm_insn ("fmove%.x %f1,%-\;move%.l %+,%0", operands);
 	  operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-	  output_asm_insn (\"move%.l %+,%0\", operands);
+	  output_asm_insn ("move%.l %+,%0", operands);
 	  operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-	  return \"move%.l %+,%0\";
+	  return "move%.l %+,%0";
 	}
       /* Must be memory destination.  */
-      return \"fmove%.x %f1,%0\";
+      return "fmove%.x %f1,%0";
     }
   return output_move_double (operands);
-}
-")
+})
 
 (define_insn ""
   [(set (match_operand:XF 0 "nonimmediate_operand" "=rm,rf,&rof<>")
 	(match_operand:XF 1 "nonimmediate_operand" "rf,m,rof<>"))]
   "! TARGET_68881 && ! TARGET_COLDFIRE"
-  "*
 {
   if (FP_REG_P (operands[0]))
     {
       if (FP_REG_P (operands[1]))
-	return \"fmove%.x %1,%0\";
+	return "fmove%.x %1,%0";
       if (REG_P (operands[1]))
 	{
 	  rtx xoperands[2];
 	  xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
-	  output_asm_insn (\"move%.l %1,%-\", xoperands);
+	  output_asm_insn ("move%.l %1,%-", xoperands);
 	  xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
-	  output_asm_insn (\"move%.l %1,%-\", xoperands);
-	  output_asm_insn (\"move%.l %1,%-\", operands);
-	  return \"fmove%.x %+,%0\";
+	  output_asm_insn ("move%.l %1,%-", xoperands);
+	  output_asm_insn ("move%.l %1,%-", operands);
+	  return "fmove%.x %+,%0";
 	}
       if (GET_CODE (operands[1]) == CONST_DOUBLE)
-        return \"fmove%.x %1,%0\";
-      return \"fmove%.x %f1,%0\";
+        return "fmove%.x %1,%0";
+      return "fmove%.x %f1,%0";
     }
   if (FP_REG_P (operands[1]))
     {
       if (REG_P (operands[0]))
         {
-          output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
+          output_asm_insn ("fmove%.x %f1,%-\;move%.l %+,%0", operands);
           operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-          output_asm_insn (\"move%.l %+,%0\", operands);
+          output_asm_insn ("move%.l %+,%0", operands);
           operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-          return \"move%.l %+,%0\";
+          return "move%.l %+,%0";
         }
       else
-        return \"fmove%.x %f1,%0\";
+        return "fmove%.x %f1,%0";
     }
   return output_move_double (operands);
-}
-")
+})
 
 (define_insn ""
   [(set (match_operand:XF 0 "nonimmediate_operand" "=r,g")
@@ -1115,37 +1103,36 @@
 ;  [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,&rf,&ro<>,!&rm,!&f")
 ;	(match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))]
   "!TARGET_COLDFIRE"
-  "*
 {
   if (FP_REG_P (operands[0]))
     {
       if (FP_REG_P (operands[1]))
-	return \"fmove%.x %1,%0\";
+	return "fmove%.x %1,%0";
       if (REG_P (operands[1]))
 	{
 	  rtx xoperands[2];
 	  xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
-	  output_asm_insn (\"move%.l %1,%-\", xoperands);
-	  output_asm_insn (\"move%.l %1,%-\", operands);
-	  return \"fmove%.d %+,%0\";
+	  output_asm_insn ("move%.l %1,%-", xoperands);
+	  output_asm_insn ("move%.l %1,%-", operands);
+	  return "fmove%.d %+,%0";
 	}
       if (GET_CODE (operands[1]) == CONST_DOUBLE)
 	return output_move_const_double (operands);
-      return \"fmove%.d %f1,%0\";
+      return "fmove%.d %f1,%0";
     }
   else if (FP_REG_P (operands[1]))
     {
       if (REG_P (operands[0]))
 	{
-	  output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
+	  output_asm_insn ("fmove%.d %f1,%-\;move%.l %+,%0", operands);
 	  operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-	  return \"move%.l %+,%0\";
+	  return "move%.l %+,%0";
 	}
       else
-        return \"fmove%.d %f1,%0\";
+        return "fmove%.d %f1,%0";
     }
   return output_move_double (operands);
-}")
+})
 
 (define_insn ""
   [(set (match_operand:DI 0 "nonimmediate_operand" "=r,g")
@@ -1170,26 +1157,24 @@
 	(truncate:QI
 	 (match_operand:SI 1 "general_src_operand" "doJS,i")))]
   ""
-  "*
 {
   if (GET_CODE (operands[0]) == REG)
     {
       /* Must clear condition codes, since the move.l bases them on
 	 the entire 32 bits, not just the desired 8 bits.  */
       CC_STATUS_INIT;
-      return \"move%.l %1,%0\";
+      return "move%.l %1,%0";
     }
   if (GET_CODE (operands[1]) == MEM)
     operands[1] = adjust_address (operands[1], QImode, 3);
-  return \"move%.b %1,%0\";
-}")
+  return "move%.b %1,%0";
+})
 
 (define_insn "trunchiqi2"
   [(set (match_operand:QI 0 "nonimmediate_operand" "=dm,d")
 	(truncate:QI
 	 (match_operand:HI 1 "general_src_operand" "doJS,i")))]
   ""
-  "*
 {
   if (GET_CODE (operands[0]) == REG
       && (GET_CODE (operands[1]) == MEM
@@ -1198,38 +1183,37 @@
       /* Must clear condition codes, since the move.w bases them on
 	 the entire 16 bits, not just the desired 8 bits.  */
       CC_STATUS_INIT;
-      return \"move%.w %1,%0\";
+      return "move%.w %1,%0";
     }
   if (GET_CODE (operands[0]) == REG)
     {
       /* Must clear condition codes, since the move.l bases them on
 	 the entire 32 bits, not just the desired 8 bits.  */
       CC_STATUS_INIT;
-      return \"move%.l %1,%0\";
+      return "move%.l %1,%0";
     }
   if (GET_CODE (operands[1]) == MEM)
     operands[1] = adjust_address (operands[1], QImode, 1);
-  return \"move%.b %1,%0\";
-}")
+  return "move%.b %1,%0";
+})
 
 (define_insn "truncsihi2"
   [(set (match_operand:HI 0 "nonimmediate_operand" "=dm,d")
 	(truncate:HI
 	 (match_operand:SI 1 "general_src_operand" "roJS,i")))]
   ""
-  "*
 {
   if (GET_CODE (operands[0]) == REG)
     {
       /* Must clear condition codes, since the move.l bases them on
 	 the entire 32 bits, not just the desired 8 bits.  */
       CC_STATUS_INIT;
-      return \"move%.l %1,%0\";
+      return "move%.l %1,%0";
     }
   if (GET_CODE (operands[1]) == MEM)
     operands[1] = adjust_address (operands[1], QImode, 2);
-  return \"move%.w %1,%0\";
-}")
+  return "move%.w %1,%0";
+})
 
 ;; zero extension instructions
 
@@ -1237,23 +1221,21 @@
   [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
 	(zero_extend:DI (match_operand:QI 1 "general_operand" "dm")))]
   ""
-  "*
 {
   CC_STATUS_INIT;
   operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-  return \"moveq %#0,%0\;moveq %#0,%2\;move%.b %1,%2\";
-}")
+  return "moveq %#0,%0\;moveq %#0,%2\;move%.b %1,%2";
+})
 
 (define_insn "zero_extendhidi2"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
 	(zero_extend:DI (match_operand:HI 1 "general_operand" "rm")))]
   ""
-  "*
 {
   CC_STATUS_INIT;
   operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-  return \"moveq %#0,%0\;moveq %#0,%2\;move%.w %1,%2\";
-}")
+  return "moveq %#0,%0\;moveq %#0,%2\;move%.w %1,%2";
+})
 
 ;; this is the canonical form for (lshiftrt:DI x 32)
 (define_expand "zero_extendsidi2"
@@ -1266,49 +1248,47 @@
   [(set (match_operand:DI 0 "nonimmediate_operand" "=r,m")
     (zero_extend:DI (match_operand:SI 1 "general_operand" "rm,r")))]
   "TARGET_COLDFIRE"
-  "*
 {
   CC_STATUS_INIT;
   if (GET_CODE (operands[0]) == REG)
     operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
   else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
-    return \"move%.l %1,%0\;clr%.l %0\";
+    return "move%.l %1,%0\;clr%.l %0";
   else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
-    return \"clr%.l %0\;move%.l %1,%0\";
+    return "clr%.l %0\;move%.l %1,%0";
   else
     operands[2] = adjust_address (operands[0], SImode, 4);
   if (GET_CODE (operands[1]) != REG || GET_CODE (operands[2]) != REG
       || REGNO (operands[1]) != REGNO (operands[2]))
-    output_asm_insn (\"move%.l %1,%2\", operands);
+    output_asm_insn ("move%.l %1,%2", operands);
   if (ADDRESS_REG_P (operands[0]))
-    return \"sub%.l %0,%0\";
+    return "sub%.l %0,%0";
   else
-    return \"clr%.l %0\";
-}")
+    return "clr%.l %0";
+})
 
 (define_insn "*zero_extendsidi2"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
     (zero_extend:DI (match_operand:SI 1 "general_operand" "rm")))]
   "!TARGET_COLDFIRE"
-  "*
 {
   CC_STATUS_INIT;
   if (GET_CODE (operands[0]) == REG)
     operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
   else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
-    return \"move%.l %1,%0\;clr%.l %0\";
+    return "move%.l %1,%0\;clr%.l %0";
   else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
-    return \"clr%.l %0\;move%.l %1,%0\";
+    return "clr%.l %0\;move%.l %1,%0";
   else
     operands[2] = adjust_address (operands[0], SImode, 4);
   if (GET_CODE (operands[1]) != REG || GET_CODE (operands[2]) != REG
       || REGNO (operands[1]) != REGNO (operands[2]))
-    output_asm_insn (\"move%.l %1,%2\", operands);
+    output_asm_insn ("move%.l %1,%2", operands);
   if (ADDRESS_REG_P (operands[0]))
-    return \"sub%.l %0,%0\";
+    return "sub%.l %0,%0";
   else
-    return \"clr%.l %0\";
-}")
+    return "clr%.l %0";
+})
 
 (define_expand "zero_extendhisi2"
   [(set (match_operand:SI 0 "register_operand" "")
@@ -1355,46 +1335,44 @@
   [(set (match_operand:SI 0 "nonimmediate_operand" "=do<>,d<")
 	(zero_extend:SI (match_operand:HI 1 "nonimmediate_src_operand" "r,mS")))]
   "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
-  "*
 {
   if (DATA_REG_P (operands[0]))
     {
       if (GET_CODE (operands[1]) == REG
 	  && REGNO (operands[0]) == REGNO (operands[1]))
-	return \"and%.l %#0xFFFF,%0\";
+	return "and%.l %#0xFFFF,%0";
       if (reg_mentioned_p (operands[0], operands[1]))
-        return \"move%.w %1,%0\;and%.l %#0xFFFF,%0\";
-      return \"clr%.l %0\;move%.w %1,%0\";
+        return "move%.w %1,%0\;and%.l %#0xFFFF,%0";
+      return "clr%.l %0\;move%.w %1,%0";
     }
   else if (GET_CODE (operands[0]) == MEM
 	   && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
-    return \"move%.w %1,%0\;clr%.w %0\";
+    return "move%.w %1,%0\;clr%.w %0";
   else if (GET_CODE (operands[0]) == MEM
 	   && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
-    return \"clr%.w %0\;move%.w %1,%0\";
+    return "clr%.w %0\;move%.w %1,%0";
   else
     {
-      output_asm_insn (\"clr%.w %0\", operands);
+      output_asm_insn ("clr%.w %0", operands);
       operands[0] = adjust_address (operands[0], HImode, 2);
-      return \"move%.w %1,%0\";
+      return "move%.w %1,%0";
     }
-}")
+})
 
 (define_insn ""
   [(set (match_operand:HI 0 "nonimmediate_operand" "=do<>,d")
 	(zero_extend:HI (match_operand:QI 1 "nonimmediate_src_operand" "d,mS")))]
   "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
-  "*
 {
   if (DATA_REG_P (operands[0]))
     {
       if (GET_CODE (operands[1]) == REG
 	  && REGNO (operands[0]) == REGNO (operands[1]))
-	return (!TARGET_COLDFIRE ? \"and%.w %#0xFF,%0\" : \"and%.l %#0xFF,%0\");
+	return (!TARGET_COLDFIRE ? "and%.w %#0xFF,%0" : "and%.l %#0xFF,%0");
       if (reg_mentioned_p (operands[0], operands[1]))
-	return (!TARGET_COLDFIRE ? \"move%.b %1,%0\;and%.w %#0xFF,%0\" 
-			     : \"move%.b %1,%0\;and%.l %#0xFF,%0\");
-      return \"clr%.w %0\;move%.b %1,%0\";
+	return (!TARGET_COLDFIRE ? "move%.b %1,%0\;and%.w %#0xFF,%0" 
+			     : "move%.b %1,%0\;and%.l %#0xFF,%0");
+      return "clr%.w %0\;move%.b %1,%0";
     }
   else if (GET_CODE (operands[0]) == MEM
 	   && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
@@ -1402,39 +1380,38 @@
       if (REGNO (XEXP (XEXP (operands[0], 0), 0))
 	  == STACK_POINTER_REGNUM)
 	{
-	  output_asm_insn (\"clr%.w %-\", operands);
+	  output_asm_insn ("clr%.w %-", operands);
 	  operands[0] = gen_rtx_MEM (GET_MODE (operands[0]),
 				     plus_constant (stack_pointer_rtx, 1));
-	  return \"move%.b %1,%0\";
+	  return "move%.b %1,%0";
 	}
       else
-	return \"move%.b %1,%0\;clr%.b %0\";
+	return "move%.b %1,%0\;clr%.b %0";
     }
   else if (GET_CODE (operands[0]) == MEM
 	   && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
-    return \"clr%.b %0\;move%.b %1,%0\";
+    return "clr%.b %0\;move%.b %1,%0";
   else
     {
-      output_asm_insn (\"clr%.b %0\", operands);
+      output_asm_insn ("clr%.b %0", operands);
       operands[0] = adjust_address (operands[0], QImode, 1);
-      return \"move%.b %1,%0\";
+      return "move%.b %1,%0";
     }
-}")
+})
 
 (define_insn ""
   [(set (match_operand:SI 0 "nonimmediate_operand" "=do<>,d")
 	(zero_extend:SI (match_operand:QI 1 "nonimmediate_src_operand" "d,mS")))]
   "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
-  "*
 {
   if (DATA_REG_P (operands[0]))
     {
       if (GET_CODE (operands[1]) == REG
 	  && REGNO (operands[0]) == REGNO (operands[1]))
-	return \"and%.l %#0xFF,%0\";
+	return "and%.l %#0xFF,%0";
       if (reg_mentioned_p (operands[0], operands[1]))
-        return \"move%.b %1,%0\;and%.l %#0xFF,%0\";
-      return \"clr%.l %0\;move%.b %1,%0\";
+        return "move%.b %1,%0\;and%.l %#0xFF,%0";
+      return "clr%.l %0\;move%.b %1,%0";
     }
   else if (GET_CODE (operands[0]) == MEM
 	   && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
@@ -1442,12 +1419,11 @@
       operands[0] = XEXP (XEXP (operands[0], 0), 0);
       return MOTOROLA ?
 #ifdef SGS
-	\"clr%.l -(%0)\;move%.b %1,3(%0)\" :
+	"clr%.l -(%0)\;move%.b %1,3(%0)" :
 #else
-	\"clr%.l -(%0)\;move%.b %1,(3,%0)\" :
+	"clr%.l -(%0)\;move%.b %1,(3,%0)" :
 #endif
-	\"clrl %0@-\;moveb %1,%0@(3)\";
-	
+	"clrl %0@-\;moveb %1,%0@(3)";
     }
   else if (GET_CODE (operands[0]) == MEM
 	   && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
@@ -1455,19 +1431,19 @@
       operands[0] = XEXP (XEXP (operands[0], 0), 0);
       return MOTOROLA ?
 #ifdef SGS
-	\"clr%.l (%0)+\;move%.b %1,-1(%0)\" :
+	"clr%.l (%0)+\;move%.b %1,-1(%0)" :
 #else
-	\"clr%.l (%0)+\;move%.b %1,(-1,%0)\" :
+	"clr%.l (%0)+\;move%.b %1,(-1,%0)" :
 #endif
-	\"clrl %0@+\;moveb %1,%0@(-1)\";
+	"clrl %0@+\;moveb %1,%0@(-1)";
     }
   else
     {
-      output_asm_insn (\"clr%.l %0\", operands);
+      output_asm_insn ("clr%.l %0", operands);
       operands[0] = adjust_address (operands[0], QImode, 3);
-      return \"move%.b %1,%0\";
+      return "move%.b %1,%0";
     }
-}")
+})
 
 ;; sign extension instructions
 
@@ -1475,45 +1451,42 @@
   [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
         (sign_extend:DI (match_operand:QI 1 "general_src_operand" "rmS")))]
   ""
-  "*
 {
   CC_STATUS_INIT;
   operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
   if (TARGET_68020 || TARGET_COLDFIRE)
-    return \"move%.b %1,%2\;extb%.l %2\;smi %0\;extb%.l %0\";
+    return "move%.b %1,%2\;extb%.l %2\;smi %0\;extb%.l %0";
   else
-    return \"move%.b %1,%2\;ext%.w %0\;ext%.l %2\;move%.l %2,%0\;smi %0\";
-}")
+    return "move%.b %1,%2\;ext%.w %0\;ext%.l %2\;move%.l %2,%0\;smi %0";
+})
 
 (define_insn "extendhidi2"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
 	(sign_extend:DI
 	 (match_operand:HI 1 "general_src_operand" "rmS")))]
   ""
-  "*
 {
   CC_STATUS_INIT;
   operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
   if (TARGET_68020 || TARGET_COLDFIRE)
-    return \"move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0\";
+    return "move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0";
   else
-    return \"move%.w %1,%2\;ext%.l %2\;smi %0\;ext%.w %0\;ext%.l %0\";
-}")
+    return "move%.w %1,%2\;ext%.l %2\;smi %0\;ext%.w %0\;ext%.l %0";
+})
 
 (define_insn "extendsidi2"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
 	(sign_extend:DI
 	 (match_operand:SI 1 "general_operand" "rm")))]
   ""
-  "*
 {
   CC_STATUS_INIT;
   operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
   if (TARGET_68020 || TARGET_COLDFIRE)
-    return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
+    return "move%.l %1,%2\;smi %0\;extb%.l %0";
   else
-    return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
-}")
+    return "move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0";
+})
 
 ;; Special case when one can avoid register clobbering, copy and test
 ;; Maybe there is a way to make that the general case, by forcing the
@@ -1524,7 +1497,6 @@
     (sign_extend:DI (plus:SI (match_operand:SI 1 "general_operand" "%rmn")
             (match_operand:SI 2 "general_operand" "rmn"))))]
   ""
-  "*
 {
   CC_STATUS_INIT;
   operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
@@ -1538,26 +1510,25 @@
     }
   if (GET_CODE (operands[1]) == REG
       && REGNO (operands[1]) == REGNO (operands[3]))
-    output_asm_insn (\"add%.l %2,%3\", operands);
+    output_asm_insn ("add%.l %2,%3", operands);
   else
-    output_asm_insn (\"move%.l %2,%3\;add%.l %1,%3\", operands);
+    output_asm_insn ("move%.l %2,%3\;add%.l %1,%3", operands);
   if (TARGET_68020 || TARGET_COLDFIRE)
-    return \"smi %0\;extb%.l %0\";
+    return "smi %0\;extb%.l %0";
   else
-    return \"smi %0\;ext%.w %0\;ext%.l %0\";
-}")
+    return "smi %0\;ext%.w %0\;ext%.l %0";
+})
 
 (define_insn "extendhisi2"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,a")
 	(sign_extend:SI
 	 (match_operand:HI 1 "nonimmediate_src_operand" "0,rmS")))]
   ""
-  "*
 {
   if (ADDRESS_REG_P (operands[0]))
-    return \"move%.w %1,%0\";
-  return \"ext%.l %0\";
-}")
+    return "move%.w %1,%0";
+  return "ext%.l %0";
+})
 
 (define_insn "extendqihi2"
   [(set (match_operand:HI 0 "nonimmediate_operand" "=d")
@@ -1585,7 +1556,6 @@
 	(float_extend:DF
 	  (match_operand:SF 1 "general_operand" "f,dmF")))]
   "TARGET_68881"
-  "*
 {
   if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
     {
@@ -1595,20 +1565,20 @@
 	     NOTICE_UPDATE_CC has already assumed that the
 	     cc will be set.  So cancel what it did.  */
 	  cc_status = cc_prev_status;
-	  return \"\";
+	  return "";
 	}
-      return \"f%&move%.x %1,%0\";
+      return "f%&move%.x %1,%0";
     }
   if (FP_REG_P (operands[0]))
-    return \"f%&move%.s %f1,%0\";
+    return "f%&move%.s %f1,%0";
   if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1]))
     {
-      output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
+      output_asm_insn ("fmove%.d %f1,%-\;move%.l %+,%0", operands);
       operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-      return \"move%.l %+,%0\";
+      return "move%.l %+,%0";
     }
-  return \"fmove%.d %f1,%0\";
-}")
+  return "fmove%.d %f1,%0";
+})
 
 ;; This cannot output into an f-reg because there is no way to be
 ;; sure of truncating in that case.
@@ -1625,12 +1595,11 @@
 	(float_truncate:SF
 	  (match_operand:DF 1 "general_operand" "fmG")))]
   "TARGET_68040_ONLY"
-  "*
 {
   if (FP_REG_P (operands[1]))
-    return \"f%$move%.x %1,%0\";
-  return \"f%$move%.d %f1,%0\";
-}")
+    return "f%$move%.x %1,%0";
+  return "f%$move%.d %f1,%0";
+})
 
 (define_insn ""
   [(set (match_operand:SF 0 "nonimmediate_operand" "=dm")
@@ -1706,11 +1675,10 @@
    (clobber (match_scratch:SI 2 "=d"))
    (clobber (match_scratch:SI 3 "=d"))]
   "TARGET_68881 && TARGET_68040"
-  "*
 {
   CC_STATUS_INIT;
-  return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.l %1,%0\;fmovem%.l %2,%!\";
-}")
+  return "fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.l %1,%0\;fmovem%.l %2,%!";
+})
 
 (define_insn "fix_truncdfhi2"
   [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
@@ -1718,11 +1686,10 @@
    (clobber (match_scratch:SI 2 "=d"))
    (clobber (match_scratch:SI 3 "=d"))]
   "TARGET_68881 && TARGET_68040"
-  "*
 {
   CC_STATUS_INIT;
-  return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.w %1,%0\;fmovem%.l %2,%!\";
-}")
+  return "fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.w %1,%0\;fmovem%.l %2,%!";
+})
 
 (define_insn "fix_truncdfqi2"
   [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
@@ -1730,11 +1697,10 @@
    (clobber (match_scratch:SI 2 "=d"))
    (clobber (match_scratch:SI 3 "=d"))]
   "TARGET_68881 && TARGET_68040"
-  "*
 {
   CC_STATUS_INIT;
-  return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.b %1,%0\;fmovem%.l %2,%!\";
-}")
+  return "fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.b %1,%0\;fmovem%.l %2,%!";
+})
 
 ;; Convert a float to a float whose value is an integer.
 ;; This is the first stage of converting it to an integer type.
@@ -1743,23 +1709,21 @@
   [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
 	(fix:DF (match_operand:DF 1 "general_operand" "fFm")))]
   "TARGET_68881 && !TARGET_68040"
-  "*
 {
   if (FP_REG_P (operands[1]))
-    return \"fintrz%.x %f1,%0\";
-  return \"fintrz%.d %f1,%0\";
-}")
+    return "fintrz%.x %f1,%0";
+  return "fintrz%.d %f1,%0";
+})
 
 (define_insn "ftruncsf2"
   [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
 	(fix:SF (match_operand:SF 1 "general_operand" "dfFm")))]
   "TARGET_68881 && !TARGET_68040"
-  "*
 {
   if (FP_REG_P (operands[1]))
-    return \"fintrz%.x %f1,%0\";
-  return \"fintrz%.s %f1,%0\";
-}")
+    return "fintrz%.x %f1,%0";
+  return "fintrz%.s %f1,%0";
+})
 
 ;; Convert a float whose value is an integer
 ;; to an actual integer.  Second stage of converting float to integer type.
@@ -1808,12 +1772,11 @@
         (match_dup 1)))
    (clobber (match_scratch:SI 2 "=d"))]
   ""
-  "*
 {
   operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
   if (REG_P (operands[1]) && REGNO (operands[1]) == REGNO (operands[0]))
     return
-    \"move%.l %1,%2\;add%.l %2,%2\;subx%.l %2,%2\;sub%.l %2,%3\;subx%.l %2,%0\";
+    "move%.l %1,%2\;add%.l %2,%2\;subx%.l %2,%2\;sub%.l %2,%3\;subx%.l %2,%0";
   if (GET_CODE (operands[1]) == REG)
     operands[4] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
   else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC
@@ -1823,17 +1786,17 @@
     operands[4] = adjust_address (operands[1], SImode, 4);
   if (GET_CODE (operands[1]) == MEM
    && GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
-    output_asm_insn (\"move%.l %4,%3\", operands);
-  output_asm_insn (\"move%.l %1,%0\;smi %2\", operands);
+    output_asm_insn ("move%.l %4,%3", operands);
+  output_asm_insn ("move%.l %1,%0\;smi %2", operands);
   if (TARGET_68020 || TARGET_COLDFIRE)
-    output_asm_insn (\"extb%.l %2\", operands);
+    output_asm_insn ("extb%.l %2", operands);
   else
-    output_asm_insn (\"ext%.w %2\;ext%.l %2\", operands);
+    output_asm_insn ("ext%.w %2\;ext%.l %2", operands);
   if (GET_CODE (operands[1]) != MEM
    || GET_CODE (XEXP (operands[1], 0)) != PRE_DEC)
-    output_asm_insn (\"move%.l %4,%3\", operands);
-  return \"sub%.l %2,%3\;subx%.l %2,%0\";
-}")
+    output_asm_insn ("move%.l %4,%3", operands);
+  return "sub%.l %2,%3\;subx%.l %2,%0";
+})
 
 (define_insn "adddi_sexthishl32"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=o,a,*d,*d")
@@ -1843,16 +1806,15 @@
         (match_operand:DI 2 "general_operand" "0,0,0,0")))
    (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
   "!TARGET_COLDFIRE"
-  "*
 {
   CC_STATUS_INIT;
   if (ADDRESS_REG_P (operands[0]))
-    return \"add%.w %1,%0\";
+    return "add%.w %1,%0";
   else if (ADDRESS_REG_P (operands[3]))
-    return \"move%.w %1,%3\;add%.l %3,%0\";
+    return "move%.w %1,%3\;add%.l %3,%0";
   else
-    return \"move%.w %1,%3\;ext%.l %3\;add%.l %3,%0\";
-} ")
+    return "move%.w %1,%3\;ext%.l %3\;add%.l %3,%0";
+})
 
 (define_insn "adddi_dilshr32"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=d,o")
@@ -1863,15 +1825,14 @@
             (const_int 32))
         (match_operand:DI 2 "general_operand" "0,0")))]
   ""
-  "*
 {
   CC_STATUS_INIT;
   if (GET_CODE (operands[0]) == REG)
     operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
   else
     operands[2] = adjust_address (operands[0], SImode, 4);
-  return \"add%.l %1,%2\;negx%.l %0\;neg%.l %0\";
-} ")
+  return "add%.l %1,%2\;negx%.l %0\;neg%.l %0";
+})
 
 (define_insn "adddi_dishl32"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
@@ -1882,15 +1843,14 @@
             (const_int 32))
         (match_operand:DI 2 "general_operand" "0,0")))]
   ""
-  "*
 {
   CC_STATUS_INIT;
   if (GET_CODE (operands[1]) == REG)
     operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
   else
     operands[1] = adjust_address (operands[1], SImode, 4);
-  return \"add%.l %1,%0\";
-} ")
+  return "add%.l %1,%0";
+})
 
 (define_insn "adddi3"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=<,o<>,d,d,d")
@@ -1898,15 +1858,14 @@
 		 (match_operand:DI 2 "general_operand" "<,d,no>,d,a")))
    (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
   ""
-  "*
 {
   if (DATA_REG_P (operands[0]))
     {
       if (DATA_REG_P (operands[2]))
-	return \"add%.l %R2,%R0\;addx%.l %2,%0\";
+	return "add%.l %R2,%R0\;addx%.l %2,%0";
       else if (GET_CODE (operands[2]) == MEM
 	  && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
-	return \"move%.l %2,%3\;add%.l %2,%R0\;addx%.l %3,%0\";
+	return "move%.l %2,%3\;add%.l %2,%R0\;addx%.l %3,%0";
       else
 	{
 	  rtx high, low;
@@ -1937,42 +1896,42 @@
 	  if (GET_CODE (operands[1]) == CONST_INT)
 	    {
 	      if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
-		return \"addq%.l %1,%R0\;addx%.l %3,%0\";
+		return "addq%.l %1,%R0\;addx%.l %3,%0";
 	      else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
 		{
 		  operands[1] = GEN_INT (-INTVAL (operands[1]));
-		  return \"subq%.l %1,%R0\;subx%.l %3,%0\";
+		  return "subq%.l %1,%R0\;subx%.l %3,%0";
 		}
 	    }
-	  return \"add%.l %1,%R0\;addx%.l %3,%0\";
+	  return "add%.l %1,%R0\;addx%.l %3,%0";
 	}
     }
   else if (GET_CODE (operands[0]) == MEM)
     {
       if (GET_CODE (operands[2]) == MEM
 	  && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
-	return \"add%.l %2,%0\;addx%.l %2,%0\";
+	return "add%.l %2,%0\;addx%.l %2,%0";
       CC_STATUS_INIT;
       if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
 	{
 	  operands[1] = gen_rtx_MEM (SImode,
 				     plus_constant (XEXP(operands[0], 0), -8));
-	  return \"move%.l %0,%3\;add%.l %R2,%0\;addx%.l %2,%3\;move%.l %3,%1\";
+	  return "move%.l %0,%3\;add%.l %R2,%0\;addx%.l %2,%3\;move%.l %3,%1";
 	}
       else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
 	{
 	  operands[1] = XEXP(operands[0], 0);
-	  return \"add%.l %R2,%0\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%1\";
+	  return "add%.l %R2,%0\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%1";
 	}
       else
 	{
 	  operands[1] = adjust_address (operands[0], SImode, 4);
-	  return \"add%.l %R2,%1\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%0\";
+	  return "add%.l %R2,%1\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%0";
 	}
     }
   else
     abort ();
-} ")
+})
 
 (define_insn "addsi_lshrsi_31"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
@@ -1980,7 +1939,6 @@
             (const_int 31))
         (match_dup 1)))]
   ""
-  "*
 {
   operands[2] = operands[0];
   operands[3] = gen_label_rtx();
@@ -1991,13 +1949,13 @@
       else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
         operands[2] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0));
     }
-  output_asm_insn (\"move%.l %1,%0\", operands);
-  output_asm_insn (MOTOROLA ? \"jbpl %l3\" : \"jpl %l3\", operands);
-  output_asm_insn (\"addq%.l %#1,%2\", operands);
-  (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
+  output_asm_insn ("move%.l %1,%0", operands);
+  output_asm_insn (MOTOROLA ? "jbpl %l3" : "jpl %l3", operands);
+  output_asm_insn ("addq%.l %#1,%2", operands);
+  (*targetm.asm_out.internal_label) (asm_out_file, "L",
 				CODE_LABEL_NUMBER (operands[3]));
-  return \"\";
-}")
+  return "";
+})
 
 (define_expand "addsi3"
   [(set (match_operand:SI 0 "nonimmediate_operand" "")
@@ -2039,7 +1997,6 @@
 	(plus:HI (match_operand:HI 1 "general_operand" "%0,0")
 		 (match_operand:HI 2 "general_src_operand" "dn,rmSn")))]
   "!TARGET_COLDFIRE"
-  "*
 {
   if (GET_CODE (operands[2]) == CONST_INT)
     {
@@ -2053,12 +2010,12 @@
 
       if (INTVAL (operands[2]) > 0
 	  && INTVAL (operands[2]) <= 8)
-	return \"addq%.w %2,%0\";
+	return "addq%.w %2,%0";
       if (INTVAL (operands[2]) < 0
 	  && INTVAL (operands[2]) >= -8)
 	{
 	  operands[2] = GEN_INT (- INTVAL (operands[2]));
-	  return \"subq%.w %2,%0\";
+	  return "subq%.w %2,%0";
 	}
       /* On the CPU32 it is faster to use two addqw instructions to
 	 add a small integer (8 < N <= 16) to a register.  
@@ -2069,20 +2026,20 @@
 	      && INTVAL (operands[2]) <= 16)
 	    {
 	      operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
-	      return \"addq%.w %#8,%0\;addq%.w %2,%0\";
+	      return "addq%.w %#8,%0\;addq%.w %2,%0";
 	    }
 	  if (INTVAL (operands[2]) < -8
 	      && INTVAL (operands[2]) >= -16)
 	    {
 	      operands[2] = GEN_INT (- INTVAL (operands[2]) - 8);
-	      return \"subq%.w %#8,%0\;subq%.w %2,%0\";
+	      return "subq%.w %#8,%0\;subq%.w %2,%0";
 	    }
 	}
       if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
-	return MOTOROLA ? \"lea (%c2,%0),%0\" : \"lea %0@(%c2),%0\";
+	return MOTOROLA ? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
     }
-  return \"add%.w %2,%0\";
-}")
+  return "add%.w %2,%0";
+})
 
 ;; These insns must use MATCH_DUP instead of the more expected
 ;; use of a matching constraint because the "output" here is also
@@ -2095,7 +2052,6 @@
 	(plus:HI (match_dup 0)
 		 (match_operand:HI 1 "general_src_operand" "dn,rmSn")))]
   "!TARGET_COLDFIRE"
-  "*
 {
   if (GET_CODE (operands[1]) == CONST_INT)
     {
@@ -2109,12 +2065,12 @@
 
       if (INTVAL (operands[1]) > 0
 	  && INTVAL (operands[1]) <= 8)
-	return \"addq%.w %1,%0\";
+	return "addq%.w %1,%0";
       if (INTVAL (operands[1]) < 0
 	  && INTVAL (operands[1]) >= -8)
 	{
 	  operands[1] = GEN_INT (- INTVAL (operands[1]));
-	  return \"subq%.w %1,%0\";
+	  return "subq%.w %1,%0";
 	}
       /* On the CPU32 it is faster to use two addqw instructions to
 	 add a small integer (8 < N <= 16) to a register. 
@@ -2125,27 +2081,26 @@
 	      && INTVAL (operands[1]) <= 16)
 	    {
 	      operands[1] = GEN_INT (INTVAL (operands[1]) - 8);
-	      return \"addq%.w %#8,%0\;addq%.w %1,%0\";
+	      return "addq%.w %#8,%0\;addq%.w %1,%0";
 	    }
 	  if (INTVAL (operands[1]) < -8
 	      && INTVAL (operands[1]) >= -16)
 	    {
 	      operands[1] = GEN_INT (- INTVAL (operands[1]) - 8);
-	      return \"subq%.w %#8,%0\;subq%.w %1,%0\";
+	      return "subq%.w %#8,%0\;subq%.w %1,%0";
 	    }
 	}
       if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
-	return MOTOROLA ? \"lea (%c1,%0),%0\" : \"lea %0@(%c1),%0\";
+	return MOTOROLA ? "lea (%c1,%0),%0" : "lea %0@(%c1),%0";
     }
-  return \"add%.w %1,%0\";
-}")
+  return "add%.w %1,%0";
+})
 
 (define_insn ""
   [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
 	(plus:HI (match_operand:HI 1 "general_src_operand" "dn,rmSn")
 		 (match_dup 0)))]
   "!TARGET_COLDFIRE"
-  "*
 {
   if (GET_CODE (operands[1]) == CONST_INT)
     {
@@ -2159,12 +2114,12 @@
 
       if (INTVAL (operands[1]) > 0
 	  && INTVAL (operands[1]) <= 8)
-	return \"addq%.w %1,%0\";
+	return "addq%.w %1,%0";
       if (INTVAL (operands[1]) < 0
 	  && INTVAL (operands[1]) >= -8)
 	{
 	  operands[1] = GEN_INT (- INTVAL (operands[1]));
-	  return \"subq%.w %1,%0\";
+	  return "subq%.w %1,%0";
 	}
       /* On the CPU32 it is faster to use two addqw instructions to
 	 add a small integer (8 < N <= 16) to a register.
@@ -2175,27 +2130,26 @@
 	      && INTVAL (operands[1]) <= 16)
 	    {
 	      operands[1] = GEN_INT (INTVAL (operands[1]) - 8);
-	      return \"addq%.w %#8,%0\;addq%.w %1,%0\";
+	      return "addq%.w %#8,%0\;addq%.w %1,%0";
 	    }
 	  if (INTVAL (operands[1]) < -8
 	      && INTVAL (operands[1]) >= -16)
 	    {
 	      operands[1] = GEN_INT (- INTVAL (operands[1]) - 8);
-	      return \"subq%.w %#8,%0\;subq%.w %1,%0\";
+	      return "subq%.w %#8,%0\;subq%.w %1,%0";
 	    }
 	}
       if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
-	return MOTOROLA ? \"lea (%c1,%0),%0\" : \"lea %0@(%c1),%0\";
+	return MOTOROLA ? "lea (%c1,%0),%0" : "lea %0@(%c1),%0";
     }
-  return \"add%.w %1,%0\";
-}")
+  return "add%.w %1,%0";
+})
 
 (define_insn "addqi3"
   [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
 	(plus:QI (match_operand:QI 1 "general_operand" "%0,0")
 		 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
   "!TARGET_COLDFIRE"
-  "*
 {
   if (GET_CODE (operands[2]) == CONST_INT)
     {
@@ -2204,22 +2158,21 @@
 
       if (INTVAL (operands[2]) > 0
 	  && INTVAL (operands[2]) <= 8)
-	return \"addq%.b %2,%0\";
+	return "addq%.b %2,%0";
       if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8)
        {
 	 operands[2] = GEN_INT (- INTVAL (operands[2]));
-	 return \"subq%.b %2,%0\";
+	 return "subq%.b %2,%0";
        }
     }
-  return \"add%.b %2,%0\";
-}")
+  return "add%.b %2,%0";
+})
 
 (define_insn ""
   [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
 	(plus:QI (match_dup 0)
 		 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
   "!TARGET_COLDFIRE"
-  "*
 {
   if (GET_CODE (operands[1]) == CONST_INT)
     {
@@ -2228,22 +2181,21 @@
 
       if (INTVAL (operands[1]) > 0
 	  && INTVAL (operands[1]) <= 8)
-	return \"addq%.b %1,%0\";
+	return "addq%.b %1,%0";
       if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
        {
 	 operands[1] = GEN_INT (- INTVAL (operands[1]));
-	 return \"subq%.b %1,%0\";
+	 return "subq%.b %1,%0";
        }
     }
-  return \"add%.b %1,%0\";
-}")
+  return "add%.b %1,%0";
+})
 
 (define_insn ""
   [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
 	(plus:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
 		 (match_dup 0)))]
   "!TARGET_COLDFIRE"
-  "*
 {
   if (GET_CODE (operands[1]) == CONST_INT)
     {
@@ -2252,15 +2204,15 @@
 
       if (INTVAL (operands[1]) > 0
 	  && INTVAL (operands[1]) <= 8)
-	return \"addq%.b %1,%0\";
+	return "addq%.b %1,%0";
       if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
        {
 	 operands[1] = GEN_INT (- INTVAL (operands[1]));
-	 return \"subq%.b %1,%0\";
+	 return "subq%.b %1,%0";
        }
     }
-  return \"add%.b %1,%0\";
-}")
+  return "add%.b %1,%0";
+})
 
 (define_expand "adddf3"
   [(set (match_operand:DF 0 "nonimmediate_operand" "")
@@ -2295,12 +2247,11 @@
 	(plus:DF (match_operand:DF 1 "general_operand" "%0")
 		 (match_operand:DF 2 "general_operand" "fmG")))]
   "TARGET_68881"
-  "*
 {
   if (REG_P (operands[2]))
-    return \"f%&add%.x %2,%0\";
-  return \"f%&add%.d %f2,%0\";
-}")
+    return "f%&add%.x %2,%0";
+  return "f%&add%.d %f2,%0";
+})
 
 (define_expand "addsf3"
   [(set (match_operand:SF 0 "nonimmediate_operand" "")
@@ -2335,12 +2286,11 @@
 	(plus:SF (match_operand:SF 1 "general_operand" "%0")
 		 (match_operand:SF 2 "general_operand" "fdmF")))]
   "TARGET_68881"
-  "*
 {
   if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
-    return \"f%$add%.x %2,%0\";
-  return \"f%$add%.s %f2,%0\";
-}")
+    return "f%$add%.x %2,%0";
+  return "f%$add%.s %f2,%0";
+})
 
 ;; subtract instructions
 
@@ -2351,16 +2301,15 @@
             (const_int 32))))
    (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
   "!TARGET_COLDFIRE"
-  "*
 {
   CC_STATUS_INIT;
   if (ADDRESS_REG_P (operands[0]))
-    return \"sub%.w %2,%0\";
+    return "sub%.w %2,%0";
   else if (ADDRESS_REG_P (operands[3]))
-    return \"move%.w %2,%3\;sub%.l %3,%0\";
+    return "move%.w %2,%3\;sub%.l %3,%0";
   else
-    return \"move%.w %2,%3\;ext%.l %3\;sub%.l %3,%0\";
-} ")
+    return "move%.w %2,%3\;ext%.l %3\;sub%.l %3,%0";
+})
 
 (define_insn "subdi_dishl32"
   [(set (match_operand:DI 0 "nonimmediate_operand" "+ro")
@@ -2368,15 +2317,14 @@
         (ashift:DI (match_operand:DI 1 "general_operand" "ro")
             (const_int 32))))]
   ""
-  "*
 {
   CC_STATUS_INIT;
   if (GET_CODE (operands[1]) == REG)
     operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
   else
     operands[1] = adjust_address (operands[1], SImode, 4);
-  return \"sub%.l %1,%0\";
-} ")
+  return "sub%.l %1,%0";
+})
 
 (define_insn "subdi3"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=<,o<>,d,d,d")
@@ -2384,16 +2332,15 @@
 		 (match_operand:DI 2 "general_operand" "<,d,no>,d,a")))
    (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
   ""
-  "*
 {
   if (DATA_REG_P (operands[0]))
     {
       if (DATA_REG_P (operands[2]))
-	return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
+	return "sub%.l %R2,%R0\;subx%.l %2,%0";
       else if (GET_CODE (operands[2]) == MEM
 	  && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
 	{
-	  return \"move%.l %2,%3\;sub%.l %2,%R0\;subx%.l %3,%0\";
+	  return "move%.l %2,%3\;sub%.l %2,%R0\;subx%.l %3,%0";
 	}
       else
 	{
@@ -2425,42 +2372,42 @@
 	  if (GET_CODE (operands[1]) == CONST_INT)
 	    {
 	      if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
-		return \"subq%.l %1,%R0\;subx%.l %3,%0\";
+		return "subq%.l %1,%R0\;subx%.l %3,%0";
 	      else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
 		{
 		  operands[1] = GEN_INT (-INTVAL (operands[1]));
-		  return \"addq%.l %1,%R0\;addx%.l %3,%0\";
+		  return "addq%.l %1,%R0\;addx%.l %3,%0";
 		}
 	    }
-	  return \"sub%.l %1,%R0\;subx%.l %3,%0\";
+	  return "sub%.l %1,%R0\;subx%.l %3,%0";
 	}
     }
   else if (GET_CODE (operands[0]) == MEM)
     {
       if (GET_CODE (operands[2]) == MEM
 	  && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
-	return \"sub%.l %2,%0\;subx%.l %2,%0\";
+	return "sub%.l %2,%0\;subx%.l %2,%0";
       CC_STATUS_INIT;
       if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
 	{
 	  operands[1]
 	    = gen_rtx_MEM (SImode, plus_constant (XEXP (operands[0], 0), -8));
-	  return \"move%.l %0,%3\;sub%.l %R2,%0\;subx%.l %2,%3\;move%.l %3,%1\";
+	  return "move%.l %0,%3\;sub%.l %R2,%0\;subx%.l %2,%3\;move%.l %3,%1";
 	}
       else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
 	{
 	  operands[1] = XEXP(operands[0], 0);
-	  return \"sub%.l %R2,%0\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%1\";
+	  return "sub%.l %R2,%0\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%1";
 	}
       else
 	{
 	  operands[1] = adjust_address (operands[0], SImode, 4);
-	  return \"sub%.l %R2,%1\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%0\";
+	  return "sub%.l %R2,%1\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%0";
 	}
     }
   else
     abort ();
-} ")
+})
 
 (define_insn "subsi3"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=m,d,a")
@@ -2538,12 +2485,11 @@
 	(minus:DF (match_operand:DF 1 "general_operand" "0")
 		  (match_operand:DF 2 "general_operand" "fmG")))]
   "TARGET_68881"
-  "*
 {
   if (REG_P (operands[2]))
-    return \"f%&sub%.x %2,%0\";
-  return \"f%&sub%.d %f2,%0\";
-}")
+    return "f%&sub%.x %2,%0";
+  return "f%&sub%.d %f2,%0";
+})
 
 (define_expand "subsf3"
   [(set (match_operand:SF 0 "nonimmediate_operand" "")
@@ -2578,12 +2524,11 @@
 	(minus:SF (match_operand:SF 1 "general_operand" "0")
 		  (match_operand:SF 2 "general_operand" "fdmF")))]
   "TARGET_68881"
-  "*
 {
   if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
-    return \"f%$sub%.x %2,%0\";
-  return \"f%$sub%.s %f2,%0\";
-}")
+    return "f%$sub%.x %2,%0";
+  return "f%$sub%.s %f2,%0";
+})
 
 ;; multiply instructions
 
@@ -2592,10 +2537,9 @@
 	(mult:HI (match_operand:HI 1 "general_operand" "%0")
 		 (match_operand:HI 2 "general_src_operand" "dmSn")))]
   ""
-  "*
 {
-  return MOTOROLA ? \"muls%.w %2,%0\" : \"muls %2,%0\";
-}")
+  return MOTOROLA ? "muls%.w %2,%0" : "muls %2,%0";
+})
 
 (define_insn "mulhisi3"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
@@ -2604,10 +2548,9 @@
 		 (sign_extend:SI
 		  (match_operand:HI 2 "nonimmediate_src_operand" "dmS"))))]
   ""
-  "*
 {
-  return MOTOROLA ? \"muls%.w %2,%0\" : \"muls %2,%0\";
-}")
+  return MOTOROLA ? "muls%.w %2,%0" : "muls %2,%0";
+})
 
 (define_insn ""
   [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
@@ -2615,10 +2558,9 @@
 		  (match_operand:HI 1 "nonimmediate_operand" "%0"))
 		 (match_operand:SI 2 "const_int_operand" "n")))]
   "INTVAL (operands[2]) >= -0x8000 && INTVAL (operands[2]) <= 0x7fff"
-  "*
 {
-  return MOTOROLA ? \"muls%.w %2,%0\" : \"muls %2,%0\";
-}")
+  return MOTOROLA ? "muls%.w %2,%0" : "muls %2,%0";
+})
 
 (define_expand "mulsi3"
   [(set (match_operand:SI 0 "nonimmediate_operand" "")
@@ -2649,10 +2591,9 @@
 		 (zero_extend:SI
 		  (match_operand:HI 2 "nonimmediate_src_operand" "dmS"))))]
   ""
-  "*
 {
-  return MOTOROLA ? \"mulu%.w %2,%0\" : \"mulu %2,%0\";
-}")
+  return MOTOROLA ? "mulu%.w %2,%0" : "mulu %2,%0";
+})
 
 (define_insn ""
   [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
@@ -2660,10 +2601,9 @@
 		  (match_operand:HI 1 "nonimmediate_operand" "%0"))
 		 (match_operand:SI 2 "const_int_operand" "n")))]
   "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 0xffff"
-  "*
 {
-  return MOTOROLA ? \"mulu%.w %2,%0\" : \"mulu %2,%0\";
-}")
+  return MOTOROLA ? "mulu%.w %2,%0" : "mulu %2,%0";
+})
 
 ;; We need a separate DEFINE_EXPAND for u?mulsidi3 to be able to use the
 ;; proper matching constraint.  This is because the matching is between
@@ -2866,19 +2806,18 @@
 	(mult:DF (match_operand:DF 1 "general_operand" "%0")
 		 (match_operand:DF 2 "general_operand" "fmG")))]
   "TARGET_68881"
-  "*
 {
   if (GET_CODE (operands[2]) == CONST_DOUBLE
       && floating_exact_log2 (operands[2]) && !TARGET_68040 && !TARGET_68060)
     {
       int i = floating_exact_log2 (operands[2]);
       operands[2] = GEN_INT (i);
-      return \"fscale%.l %2,%0\";
+      return "fscale%.l %2,%0";
     }
   if (REG_P (operands[2]))
-    return \"f%&mul%.x %2,%0\";
-  return \"f%&mul%.d %f2,%0\";
-}")
+    return "f%&mul%.x %2,%0";
+  return "f%&mul%.d %f2,%0";
+})
 
 (define_expand "mulsf3"
   [(set (match_operand:SF 0 "nonimmediate_operand" "")
@@ -2892,52 +2831,48 @@
 	(mult:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
 		 (match_operand:SF 1 "general_operand" "0")))]
   "TARGET_68881"
-  "*
 {
   return (TARGET_68040_ONLY
-          ? \"fsmul%.l %2,%0\"
-          : \"fsglmul%.l %2,%0\");
-}")
+          ? "fsmul%.l %2,%0"
+          : "fsglmul%.l %2,%0");
+})
 
 (define_insn ""
   [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
 	(mult:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
 		 (match_operand:SF 1 "general_operand" "0")))]
   "TARGET_68881"
-  "*
 {
   return (TARGET_68040_ONLY
-          ? \"fsmul%.w %2,%0\"
-          : \"fsglmul%.w %2,%0\");
-}")
+          ? "fsmul%.w %2,%0"
+          : "fsglmul%.w %2,%0");
+})
 
 (define_insn ""
   [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
 	(mult:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
 		 (match_operand:SF 1 "general_operand" "0")))]
   "TARGET_68881"
-  "*
 {
   return (TARGET_68040_ONLY
-          ? \"fsmul%.b %2,%0\"
-          : \"fsglmul%.b %2,%0\");
-}")
+          ? "fsmul%.b %2,%0"
+          : "fsglmul%.b %2,%0");
+})
 
 (define_insn ""
   [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
 	(mult:SF (match_operand:SF 1 "general_operand" "%0")
 		 (match_operand:SF 2 "general_operand" "fdmF")))]
   "TARGET_68881"
-  "*
 {
   if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
     return (TARGET_68040_ONLY
-	    ? \"fsmul%.x %2,%0\"
-	    : \"fsglmul%.x %2,%0\");
+	    ? "fsmul%.x %2,%0"
+	    : "fsglmul%.x %2,%0");
   return (TARGET_68040_ONLY
-	  ? \"fsmul%.s %f2,%0\"
-	  : \"fsglmul%.s %f2,%0\");
-}")
+	  ? "fsmul%.s %f2,%0"
+	  : "fsglmul%.s %f2,%0");
+})
 
 ;; divide instructions
 
@@ -2974,12 +2909,11 @@
 	(div:DF (match_operand:DF 1 "general_operand" "0")
 		(match_operand:DF 2 "general_operand" "fmG")))]
   "TARGET_68881"
-  "*
 {
   if (REG_P (operands[2]))
-    return \"f%&div%.x %2,%0\";
-  return \"f%&div%.d %f2,%0\";
-}")
+    return "f%&div%.x %2,%0";
+  return "f%&div%.d %f2,%0";
+})
 
 (define_expand "divsf3"
   [(set (match_operand:SF 0 "nonimmediate_operand" "")
@@ -2993,52 +2927,48 @@
 	(div:SF (match_operand:SF 1 "general_operand" "0")
 		(float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
   "TARGET_68881"
-  "*
 {
   return (TARGET_68040_ONLY
-          ? \"fsdiv%.l %2,%0\"
-          : \"fsgldiv%.l %2,%0\");
-}")
+          ? "fsdiv%.l %2,%0"
+          : "fsgldiv%.l %2,%0");
+})
 
 (define_insn ""
   [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
 	(div:SF (match_operand:SF 1 "general_operand" "0")
 		(float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
   "TARGET_68881"
-  "*
 {
   return (TARGET_68040_ONLY
-          ? \"fsdiv%.w %2,%0\"
-          : \"fsgldiv%.w %2,%0\");
-}")
+          ? "fsdiv%.w %2,%0"
+          : "fsgldiv%.w %2,%0");
+})
 
 (define_insn ""
   [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
 	(div:SF (match_operand:SF 1 "general_operand" "0")
 		(float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
   "TARGET_68881"
-  "*
 {
   return (TARGET_68040_ONLY
-          ? \"fsdiv%.b %2,%0\"
-          : \"fsgldiv%.b %2,%0\");
-}")
+          ? "fsdiv%.b %2,%0"
+          : "fsgldiv%.b %2,%0");
+})
 
 (define_insn ""
   [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
 	(div:SF (match_operand:SF 1 "general_operand" "0")
 		(match_operand:SF 2 "general_operand" "fdmF")))]
   "TARGET_68881"
-  "*
 {
   if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
     return (TARGET_68040_ONLY
-	    ? \"fsdiv%.x %2,%0\"
-	    : \"fsgldiv%.x %2,%0\");
+	    ? "fsdiv%.x %2,%0"
+	    : "fsgldiv%.x %2,%0");
   return (TARGET_68040_ONLY
-	  ? \"fsdiv%.s %f2,%0\"
-	  : \"fsgldiv%.s %f2,%0\");
-}")
+	  ? "fsdiv%.s %f2,%0"
+	  : "fsgldiv%.s %f2,%0");
+})
 
 ;; Remainder instructions.
 
@@ -3059,15 +2989,14 @@
    (set (match_operand:SI 3 "nonimmediate_operand" "=&d")
 	(mod:SI (match_dup 1) (match_dup 2)))]
   "TARGET_CF_HWDIV"
-  "*
 {
   if (find_reg_note (insn, REG_UNUSED, operands[3]))
-    return \"divs%.l %2,%0\";
+    return "divs%.l %2,%0";
   else if (find_reg_note (insn, REG_UNUSED, operands[0]))
-    return \"rems%.l %2,%3:%0\";
+    return "rems%.l %2,%3:%0";
   else
-    return \"rems%.l %2,%3:%0\;divs%.l %2,%0\";
-}")
+    return "rems%.l %2,%3:%0\;divs%.l %2,%0";
+})
 
 (define_insn ""
   [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
@@ -3076,13 +3005,12 @@
    (set (match_operand:SI 3 "nonimmediate_operand" "=d")
 	(mod:SI (match_dup 1) (match_dup 2)))]
   "TARGET_68020"
-  "*
 {
   if (find_reg_note (insn, REG_UNUSED, operands[3]))
-    return \"divs%.l %2,%0\";
+    return "divs%.l %2,%0";
   else
-    return \"divsl%.l %2,%3:%0\";
-}")
+    return "divsl%.l %2,%3:%0";
+})
 
 (define_expand "udivmodsi4"
   [(parallel
@@ -3101,15 +3029,14 @@
    (set (match_operand:SI 3 "nonimmediate_operand" "=&d")
 	(umod:SI (match_dup 1) (match_dup 2)))]
   "TARGET_CF_HWDIV"
-  "*
 {
   if (find_reg_note (insn, REG_UNUSED, operands[3]))
-    return \"divu%.l %2,%0\";
+    return "divu%.l %2,%0";
   else if (find_reg_note (insn, REG_UNUSED, operands[0]))
-    return \"remu%.l %2,%3:%0\";
+    return "remu%.l %2,%3:%0";
   else
-    return \"remu%.l %2,%3:%0\;divu%.l %2,%0\";
-}")
+    return "remu%.l %2,%3:%0\;divu%.l %2,%0";
+})
 
 (define_insn ""
   [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
@@ -3118,13 +3045,12 @@
    (set (match_operand:SI 3 "nonimmediate_operand" "=d")
 	(umod:SI (match_dup 1) (match_dup 2)))]
   "TARGET_68020 && !TARGET_COLDFIRE"
-  "*
 {
   if (find_reg_note (insn, REG_UNUSED, operands[3]))
-    return \"divu%.l %2,%0\";
+    return "divu%.l %2,%0";
   else
-    return \"divul%.l %2,%3:%0\";
-}")
+    return "divul%.l %2,%3:%0";
+})
 
 (define_insn "divmodhi4"
   [(set (match_operand:HI 0 "nonimmediate_operand" "=d")
@@ -3133,20 +3059,19 @@
    (set (match_operand:HI 3 "nonimmediate_operand" "=d")
 	(mod:HI (match_dup 1) (match_dup 2)))]
   "!TARGET_COLDFIRE || TARGET_CF_HWDIV"
-  "*
 {
   output_asm_insn (MOTOROLA ?
-    \"ext%.l %0\;divs%.w %2,%0\" :
-    \"extl %0\;divs %2,%0\",
+    "ext%.l %0\;divs%.w %2,%0" :
+    "extl %0\;divs %2,%0",
     operands);
   if (!find_reg_note(insn, REG_UNUSED, operands[3]))
     {
       CC_STATUS_INIT;
-      return \"move%.l %0,%3\;swap %3\";
+      return "move%.l %0,%3\;swap %3";
     }
   else
-    return \"\";
-}")
+    return "";
+})
 
 (define_insn "udivmodhi4"
   [(set (match_operand:HI 0 "nonimmediate_operand" "=d")
@@ -3155,20 +3080,19 @@
    (set (match_operand:HI 3 "nonimmediate_operand" "=d")
 	(umod:HI (match_dup 1) (match_dup 2)))]
   "!TARGET_COLDFIRE || TARGET_CF_HWDIV"
-  "*
 {
   output_asm_insn (MOTOROLA ?
-    \"and%.l %#0xFFFF,%0\;divu%.w %2,%0\" :
-    \"and%.l %#0xFFFF,%0\;divu %2,%0\",
+    "and%.l %#0xFFFF,%0\;divu%.w %2,%0" :
+    "and%.l %#0xFFFF,%0\;divu %2,%0",
     operands);
   if (!find_reg_note(insn, REG_UNUSED, operands[3]))
     {
       CC_STATUS_INIT;
-      return \"move%.l %0,%3\;swap %3\";
+      return "move%.l %0,%3\;swap %3";
     }
   else
-    return \"\";
-}")
+    return "";
+})
 
 ;; logical-and instructions
 
@@ -3178,7 +3102,6 @@
 	(and:DI (match_operand:DI 1 "general_operand" "%0,0")
 		(match_operand:DI 2 "general_operand" "dn,don")))]
   "!TARGET_COLDFIRE"
-  "*
 {
   CC_STATUS_INIT;
   /* We can get CONST_DOUBLE, but also const1_rtx etc.  */
@@ -3191,7 +3114,7 @@
       switch (INTVAL (hi))
 	{
 	  case 0 :
-	    output_asm_insn (\"clr%.l %0\", operands);
+	    output_asm_insn ("clr%.l %0", operands);
 	    break;
 	  case -1 :
 	    break;
@@ -3211,7 +3134,7 @@
       switch (INTVAL (lo))
 	{
 	  case 0 :
-	    output_asm_insn (\"clr%.l %0\", operands);
+	    output_asm_insn ("clr%.l %0", operands);
 	    break;
 	  case -1 :
 	    break;
@@ -3224,20 +3147,20 @@
 	    output_asm_insn (output_andsi3 (xoperands), xoperands);
 	    }
 	}
-      return \"\";
+      return "";
     }
   if (GET_CODE (operands[0]) != REG)
     {
       operands[1] = adjust_address (operands[0], SImode, 4);
-      return \"and%.l %2,%0\;and%.l %R2,%1\";
+      return "and%.l %2,%0\;and%.l %R2,%1";
     }
   if (GET_CODE (operands[2]) != REG)
     {
       operands[1] = adjust_address (operands[2], SImode, 4);
-      return \"and%.l %2,%0\;and%.l %1,%R0\";
+      return "and%.l %2,%0\;and%.l %1,%R0";
     }
-  return \"and%.l %2,%0\;and%.l %R2,%R0\";
-}")
+  return "and%.l %2,%0\;and%.l %R2,%R0";
+})
 
 ;; Prevent AND from being made with sp.  This doesn't exist in the machine
 ;; and reload will cause inefficient code.  Since sp is a FIXED_REG, we
@@ -3255,10 +3178,9 @@
 	(and:SI (match_operand:SI 1 "general_operand" "%0,0")
 		(match_operand:SI 2 "general_src_operand" "dKT,dmSM")))]
   "!TARGET_COLDFIRE"
-  "*
 {
   return output_andsi3 (operands);
-}")
+})
 
 (define_insn "andsi3_5200"
   [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
@@ -3316,7 +3238,6 @@
     (ior:DI (zero_extend:DI (match_operand 1 "general_operand" "dn,dmn"))
         (match_operand:DI 2 "general_operand" "0,0")))]
   "!TARGET_COLDFIRE"
-  "*
 {
   int byte_mode;
 
@@ -3326,16 +3247,16 @@
   else
     operands[0] = adjust_address (operands[0], SImode, 4);
   if (GET_MODE (operands[1]) == SImode)
-    return \"or%.l %1,%0\";
+    return "or%.l %1,%0";
   byte_mode = (GET_MODE (operands[1]) == QImode);
   if (GET_CODE (operands[0]) == MEM)
     operands[0] = adjust_address (operands[0], byte_mode ? QImode : HImode,
 				  byte_mode ? 3 : 2);
   if (byte_mode)
-    return \"or%.b %1,%0\";
+    return "or%.b %1,%0";
   else
-    return \"or%.w %1,%0\";
-}")
+    return "or%.w %1,%0";
+})
 
 ;; "iordi3" is mainly here to help combine().
 (define_insn "iordi3"
@@ -3343,7 +3264,6 @@
 	(ior:DI (match_operand:DI 1 "general_operand" "%0,0")
 		(match_operand:DI 2 "general_operand" "dn,don")))]
   "!TARGET_COLDFIRE"
-  "*
 {
   CC_STATUS_INIT;
   /* We can get CONST_DOUBLE, but also const1_rtx etc.  */
@@ -3360,7 +3280,7 @@
 	  case -1 :
 	    /* FIXME : a scratch register would be welcome here if operand[0]
 	       is not a register */
-	    output_asm_insn (\"move%.l %#-1,%0\", operands);
+	    output_asm_insn ("move%.l %#-1,%0", operands);
 	    break;
 	  default :
 	    {
@@ -3382,7 +3302,7 @@
 	  case -1 :
 	    /* FIXME : a scratch register would be welcome here if operand[0]
 	       is not a register */
-	    output_asm_insn (\"move%.l %#-1,%0\", operands);
+	    output_asm_insn ("move%.l %#-1,%0", operands);
 	    break;
 	  default :
 	    {
@@ -3393,20 +3313,20 @@
 	    output_asm_insn (output_iorsi3 (xoperands), xoperands);
 	    }
 	}
-      return \"\";
+      return "";
     }
   if (GET_CODE (operands[0]) != REG)
     {
       operands[1] = adjust_address (operands[0], SImode, 4);
-      return \"or%.l %2,%0\;or%.l %R2,%1\";
+      return "or%.l %2,%0\;or%.l %R2,%1";
     }
   if (GET_CODE (operands[2]) != REG)
     {
       operands[1] = adjust_address (operands[2], SImode, 4);
-      return \"or%.l %2,%0\;or%.l %1,%R0\";
+      return "or%.l %2,%0\;or%.l %1,%R0";
     }
-  return \"or%.l %2,%0\;or%.l %R2,%R0\";
-}")
+  return "or%.l %2,%0\;or%.l %R2,%R0";
+})
 
 (define_expand "iorsi3"
   [(set (match_operand:SI 0 "nonimmediate_operand" "")
@@ -3420,10 +3340,9 @@
 	(ior:SI (match_operand:SI 1 "general_operand" "%0,0")
                 (match_operand:SI 2 "general_src_operand" "dKT,dmSMT")))]
   "! TARGET_COLDFIRE"
-  "*
 {
   return output_iorsi3 (operands);
-}")
+})
 
 (define_insn "iorsi3_5200"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=m,d")
@@ -3483,23 +3402,21 @@
         (ashift:SI (match_operand:SI 2 "general_operand" "or")
             (const_int 16))))]
   ""
-  "*
 {
   CC_STATUS_INIT;
   if (GET_CODE (operands[2]) != REG)
       operands[2] = adjust_address (operands[2], HImode, 2);
   if (GET_CODE (operands[2]) != REG
   || REGNO (operands[2]) != REGNO (operands[0]))
-    output_asm_insn (\"move%.w %2,%0\", operands);
-  return \"swap %0\;mov%.w %1,%0\";
-}")
+    output_asm_insn ("move%.w %2,%0", operands);
+  return "swap %0\;mov%.w %1,%0";
+})
 
 (define_insn "iorsi_zext"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=o,d")
     (ior:SI (zero_extend:SI (match_operand 1 "general_operand" "dn,dmn"))
         (match_operand:SI 2 "general_operand" "0,0")))]
   "!TARGET_COLDFIRE"
-  "*
 {
   int byte_mode;
 
@@ -3509,10 +3426,10 @@
     operands[0] = adjust_address (operands[0], byte_mode ? QImode : HImode,
 				  byte_mode ? 3 : 2);
   if (byte_mode)
-    return \"or%.b %1,%0\";
+    return "or%.b %1,%0";
   else
-    return \"or%.w %1,%0\";
-}")
+    return "or%.w %1,%0";
+})
 
 ;; xor instructions
 
@@ -3522,7 +3439,6 @@
 	(xor:DI (match_operand:DI 1 "general_operand" "%0")
 		(match_operand:DI 2 "general_operand" "dn")))]
   "!TARGET_COLDFIRE"
-  "*
 {
   CC_STATUS_INIT;
   /* We can get CONST_DOUBLE, but also const1_rtx etc.  */
@@ -3538,7 +3454,7 @@
 	  case 0 :
 	    break;
 	  case -1 :
-	    output_asm_insn (\"not%.l %0\", operands);
+	    output_asm_insn ("not%.l %0", operands);
 	    break;
 	  default :
 	    /* FIXME : a scratch register would be welcome here if
@@ -3560,7 +3476,7 @@
 	  case 0 :
 	    break;
 	  case -1 :
-	    output_asm_insn (\"not%.l %0\", operands);
+	    output_asm_insn ("not%.l %0", operands);
 	    break;
 	  default :
 	    /* FIXME : a scratch register would be welcome here if
@@ -3575,20 +3491,20 @@
 	    output_asm_insn (output_xorsi3 (xoperands), xoperands);
 	    }
 	}
-      return \"\";
+      return "";
     }
   if (GET_CODE (operands[0]) != REG)
     {
       operands[1] = adjust_address (operands[0], SImode, 4);
-      return \"eor%.l %2,%0\;eor%.l %R2,%1\";
+      return "eor%.l %2,%0\;eor%.l %R2,%1";
     }
   if (GET_CODE (operands[2]) != REG)
     {
       operands[1] = adjust_address (operands[2], SImode, 4);
-      return \"eor%.l %2,%0\;eor%.l %1,%R0\";
+      return "eor%.l %2,%0\;eor%.l %1,%R0";
     }
-  return \"eor%.l %2,%0\;eor%.l %R2,%R0\";
-}")
+  return "eor%.l %2,%0\;eor%.l %R2,%R0";
+})
 
 (define_expand "xorsi3"
   [(set (match_operand:SI 0 "nonimmediate_operand" "")
@@ -3603,10 +3519,9 @@
                 (match_operand:SI 2 "general_operand" "di,dKT")))]
 
   "!TARGET_COLDFIRE"
-  "*
 {
   return output_xorsi3 (operands);
-}")
+})
 
 (define_insn "xorsi3_5200"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=dm,d")
@@ -3676,29 +3591,27 @@
   [(set (match_operand:DI 0 "nonimmediate_operand" "=<,do,!*a")
 	(neg:DI (match_operand:DI 1 "general_operand" "0,0,0")))]
   "!TARGET_COLDFIRE"
-  "*
 {
   if (which_alternative == 0)
-    return \"neg%.l %0\;negx%.l %0\";
+    return "neg%.l %0\;negx%.l %0";
   if (GET_CODE (operands[0]) == REG)
     operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
   else
     operands[1] = adjust_address (operands[0], SImode, 4);
   if (ADDRESS_REG_P (operands[0]))
-    return \"exg %/d0,%1\;neg%.l %/d0\;exg %/d0,%1\;exg %/d0,%0\;negx%.l %/d0\;exg %/d0,%0\";
+    return "exg %/d0,%1\;neg%.l %/d0\;exg %/d0,%1\;exg %/d0,%0\;negx%.l %/d0\;exg %/d0,%0";
   else
-    return \"neg%.l %1\;negx%.l %0\";
-} ")
+    return "neg%.l %1\;negx%.l %0";
+})
 
 (define_insn "negdi2_5200"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
 	(neg:DI (match_operand:DI 1 "general_operand" "0")))]
   "TARGET_COLDFIRE"
-  "*
 {
   operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-  return \"neg%.l %1\;negx%.l %0\";
-} ")
+  return "neg%.l %1\;negx%.l %0";
+})
 
 (define_expand "negsi2"
   [(set (match_operand:SI 0 "nonimmediate_operand" "")
@@ -3782,17 +3695,16 @@
   [(set (match_operand:SF 0 "nonimmediate_operand" "=f,d")
 	(neg:SF (match_operand:SF 1 "general_operand" "fdmF,0")))]
   "TARGET_68881"
-  "*
 {
   if (DATA_REG_P (operands[0]))
     {
       operands[1] = GEN_INT (31);
-      return \"bchg %1,%0\";
+      return "bchg %1,%0";
     }
   if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
-    return \"f%$neg%.x %1,%0\";
-  return \"f%$neg%.s %f1,%0\";
-}")
+    return "f%$neg%.x %1,%0";
+  return "f%$neg%.s %f1,%0";
+})
 
 (define_expand "negdf2"
   [(set (match_operand:DF 0 "nonimmediate_operand" "")
@@ -3832,17 +3744,16 @@
   [(set (match_operand:DF 0 "nonimmediate_operand" "=f,d")
 	(neg:DF (match_operand:DF 1 "general_operand" "fmF,0")))]
   "TARGET_68881"
-  "*
 {
   if (DATA_REG_P (operands[0]))
     {
       operands[1] = GEN_INT (31);
-      return \"bchg %1,%0\";
+      return "bchg %1,%0";
     }
   if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
-    return \"f%&neg%.x %1,%0\";
-  return \"f%&neg%.d %f1,%0\";
-}")
+    return "f%&neg%.x %1,%0";
+  return "f%&neg%.d %f1,%0";
+})
 
 ;; Sqrt instruction for the 68881
 
@@ -3850,25 +3761,23 @@
   [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
 	(sqrt:SF (match_operand:SF 1 "general_operand" "fm")))]
   "TARGET_68881"
-  "*
 {
   if (FP_REG_P (operands[1]))
-    return \"f%$sqrt%.x %1,%0\";
+    return "f%$sqrt%.x %1,%0";
   else
-    return \"f%$sqrt%.s %1,%0\";
-}")
+    return "f%$sqrt%.s %1,%0";
+})
 
 (define_insn "sqrtdf2"
   [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
 	(sqrt:DF (match_operand:DF 1 "general_operand" "fm")))]
   "TARGET_68881"
-  "*
 {
   if (FP_REG_P (operands[1]))
-    return \"f%&sqrt%.x %1,%0\";
+    return "f%&sqrt%.x %1,%0";
   else
-    return \"f%&sqrt%.d %1,%0\";
-}")
+    return "f%&sqrt%.d %1,%0";
+})
 
 ;; Absolute value instructions
 ;; If using software floating point, just zero the sign bit.
@@ -3904,12 +3813,11 @@
   [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
 	(abs:SF (match_operand:SF 1 "general_operand" "fdmF")))]
   "TARGET_68881"
-  "*
 {
   if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
-    return \"f%$abs%.x %1,%0\";
-  return \"f%$abs%.s %f1,%0\";
-}")
+    return "f%$abs%.x %1,%0";
+  return "f%$abs%.s %f1,%0";
+})
 
 (define_expand "absdf2"
   [(set (match_operand:DF 0 "nonimmediate_operand" "")
@@ -3949,12 +3857,11 @@
   [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
 	(abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
   "TARGET_68881"
-  "*
 {
   if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
-    return \"f%&abs%.x %1,%0\";
-  return \"f%&abs%.d %f1,%0\";
-}")
+    return "f%&abs%.x %1,%0";
+  return "f%&abs%.d %f1,%0";
+})
 
 ;; one complement instructions
 
@@ -3963,7 +3870,6 @@
   [(set (match_operand:DI 0 "nonimmediate_operand" "=dm")
 	(not:DI (match_operand:DI 1 "general_operand" "0")))]
   "!TARGET_COLDFIRE"
-  "*
 {
   CC_STATUS_INIT;
   if (GET_CODE (operands[0]) == REG)
@@ -3973,8 +3879,8 @@
     operands[1] = operands[0];
   else
     operands[1] = adjust_address (operands[0], SImode, 4);
-  return \"not%.l %1\;not%.l %0\";
-}")
+  return "not%.l %1\;not%.l %0";
+})
 
 (define_expand "one_cmplsi2"
   [(set (match_operand:SI 0 "nonimmediate_operand" "")
@@ -4035,7 +3941,6 @@
         [(match_operand:SI 1 "general_operand" "rm")])
       (const_int 32)))]
   ""
-  "*
 {
   CC_STATUS_INIT;
   if (GET_CODE (operands[0]) == REG)
@@ -4043,10 +3948,10 @@
   else
     operands[2] = adjust_address (operands[0], SImode, 4);
   if (ADDRESS_REG_P (operands[0]))
-    return \"move%.l %1,%0\;sub%.l %2,%2\";
+    return "move%.l %1,%0\;sub%.l %2,%2";
   else
-    return \"move%.l %1,%0\;clr%.l %2\";
-} ")
+    return "move%.l %1,%0\;clr%.l %2";
+})
 
 (define_insn "ashldi_sexthi"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=m,a*d")
@@ -4054,33 +3959,31 @@
         (const_int 32)))
     (clobber (match_scratch:SI 2 "=a,X"))]
   ""
-  "*
 {
   CC_STATUS_INIT;
   if (GET_CODE (operands[0]) == MEM)
     {
     if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
-      return \"clr%.l %0\;move%.w %1,%2\;move%.l %2,%0\";
+      return "clr%.l %0\;move%.w %1,%2\;move%.l %2,%0";
     else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
-      return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %0\";
+      return "move%.w %1,%2\;move%.l %2,%0\;clr%.l %0";
     else
       {
 	operands[3] = adjust_address (operands[0], SImode, 4);
-	return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %3\";
+	return "move%.w %1,%2\;move%.l %2,%0\;clr%.l %3";
       }
     }
   else if (DATA_REG_P (operands[0]))
-    return \"move%.w %1,%0\;ext%.l %0\;clr%.l %R0\";
+    return "move%.w %1,%0\;ext%.l %0\;clr%.l %R0";
   else
-    return \"move%.w %1,%0\;sub%.l %R0,%R0\";
-} ")
+    return "move%.w %1,%0\;sub%.l %R0,%R0";
+})
 
 (define_insn "ashldi_const32"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
 	(ashift:DI (match_operand:DI 1 "general_operand" "ro")
 		     (const_int 32)))]
   ""
-  "*
 {
   CC_STATUS_INIT;
   if (GET_CODE (operands[1]) == REG)
@@ -4090,16 +3993,16 @@
   if (GET_CODE (operands[0]) == REG)
     operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
   else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
-    return \"clr%.l %0\;move%.l %3,%0\";
+    return "clr%.l %0\;move%.l %3,%0";
   else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
-    return \"move%.l %3,%0\;clr%.l %0\";
+    return "move%.l %3,%0\;clr%.l %0";
   else
     operands[2] = adjust_address (operands[0], SImode, 4);
   if (ADDRESS_REG_P (operands[2]))
-    return \"move%.l %3,%0\;sub%.l %2,%2\";
+    return "move%.l %3,%0\;sub%.l %2,%2";
   else
-    return \"move%.l %3,%0\;clr%.l %2\";
-} ")
+    return "move%.l %3,%0\;clr%.l %2";
+})
 
 ;; The predicate below must be general_operand, because ashldi3 allows that
 (define_insn "ashldi_const"
@@ -4110,29 +4013,28 @@
     && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
 	|| INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
 	|| (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
-  "*
 {
   operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
   if (INTVAL (operands[2]) == 1)
-    return \"add%.l %1,%1\;addx%.l %0,%0\";
+    return "add%.l %1,%1\;addx%.l %0,%0";
   else if (INTVAL (operands[2]) == 8)
-    return \"rol%.l %#8,%1\;rol%.l %#8,%0\;move%.b %1,%0\;clr%.b %1\";
+    return "rol%.l %#8,%1\;rol%.l %#8,%0\;move%.b %1,%0\;clr%.b %1";
   else if (INTVAL (operands[2]) == 16)
-    return \"swap %1\;swap %0\;move%.w %1,%0\;clr%.w %1\";
+    return "swap %1\;swap %0\;move%.w %1,%0\;clr%.w %1";
   else if (INTVAL (operands[2]) == 48)
-    return \"mov%.l %1,%0\;swap %0\;clr%.l %1\;clr%.w %0\";
+    return "mov%.l %1,%0\;swap %0\;clr%.l %1\;clr%.w %0";
   else if (INTVAL (operands[2]) == 2)
-    return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
+    return "add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0";
   else if (INTVAL (operands[2]) == 3)
-    return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
+    return "add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0";
   else /* 32 < INTVAL (operands[2]) <= 63 */
     {
       operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
-      output_asm_insn (INTVAL (operands[2]) <= 8 ? \"asl%.l %2,%1\" :
-			\"moveq %2,%0\;asl%.l %0,%1\", operands);
-      return \"mov%.l %1,%0\;moveq %#0,%1\";
+      output_asm_insn (INTVAL (operands[2]) <= 8 ? "asl%.l %2,%1" :
+			"moveq %2,%0\;asl%.l %0,%1", operands);
+      return "mov%.l %1,%0\;moveq %#0,%1";
     }
-} ")
+})
 
 (define_expand "ashldi3"
   [(set (match_operand:DI 0 "nonimmediate_operand" "")
@@ -4157,11 +4059,10 @@
 	(ashift:SI (match_operand:SI 1 "register_operand" "0")
 		   (const_int 16)))]
   "!TARGET_68060"
-  "*
 {
   CC_STATUS_INIT;
-  return \"swap %0\;clr%.w %0\";
-}")
+  return "swap %0\;clr%.w %0";
+})
 
 ;; ashift patterns : use lsl instead of asl, because lsl always clears the
 ;; overflow bit, so we must not set CC_NO_OVERFLOW.
@@ -4174,28 +4075,26 @@
 		   (match_operand:SI 2 "const_int_operand" "n")))]
   "(! TARGET_68020 && !TARGET_COLDFIRE
     && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
-  "*
 {
   CC_STATUS_INIT;
 
   operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
-  return \"lsl%.w %2,%0\;swap %0\;clr%.w %0\";
-}")
+  return "lsl%.w %2,%0\;swap %0\;clr%.w %0";
+})
 
 (define_insn "ashlsi3"
   [(set (match_operand:SI 0 "register_operand" "=d")
 	(ashift:SI (match_operand:SI 1 "register_operand" "0")
 		   (match_operand:SI 2 "general_operand" "dI")))]
   ""
-  "*
 {
   if (operands[2] == const1_rtx)
     {
       cc_status.flags = CC_NO_OVERFLOW;
-      return \"add%.l %0,%0\";
+      return "add%.l %0,%0";
     }
-  return \"lsl%.l %2,%0\";
-}")
+  return "lsl%.l %2,%0";
+})
 
 (define_insn "ashlhi3"
   [(set (match_operand:HI 0 "register_operand" "=d")
@@ -4242,48 +4141,44 @@
 		     (match_operand:SI 2 "const_int_operand" "n")))]
   "(! TARGET_68020 && !TARGET_COLDFIRE
     && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
-  "*
 {
   operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
-  return \"swap %0\;asr%.w %2,%0\;ext%.l %0\";
-}")
+  return "swap %0\;asr%.w %2,%0\;ext%.l %0";
+})
 
 (define_insn "subreghi1ashrdi_const32"
   [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
     (subreg:HI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
             (const_int 32)) 6))]
   ""
-  "*
 {
   if (GET_CODE (operands[1]) != REG)
     operands[1] = adjust_address (operands[1], HImode, 2);
-  return \"move%.w %1,%0\";
-} ")
+  return "move%.w %1,%0";
+})
 
 (define_insn "subregsi1ashrdi_const32"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
     (subreg:SI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
             (const_int 32)) 4))]
   ""
-  "*
 {
-  return \"move%.l %1,%0\";
-} ")
+  return "move%.l %1,%0";
+})
 
 (define_insn "ashrdi_const32"
   [(set (match_operand:DI 0 "register_operand" "=d")
 	(ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
 		     (const_int 32)))]
   ""
-  "*
 {
   CC_STATUS_INIT;
   operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
   if (TARGET_68020)
-    return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
+    return "move%.l %1,%2\;smi %0\;extb%.l %0";
   else
-    return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
-} ")
+    return "move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0";
+})
 
 (define_insn "ashrdi_const32_mem"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=o,<")
@@ -4291,7 +4186,6 @@
 		     (const_int 32)))
    (clobber (match_scratch:SI 2 "=d,d"))]
   ""
-  "*
 {
   CC_STATUS_INIT;
   if (which_alternative == 1)
@@ -4299,10 +4193,10 @@
   else
     operands[3] = adjust_address (operands[0], SImode, 4);
   if (TARGET_68020)
-    return \"move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0\";
+    return "move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0";
   else
-    return \"move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0\";
-} ")
+    return "move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0";
+})
 
 ;; The predicate below must be general_operand, because ashrdi3 allows that
 (define_insn "ashrdi_const"
@@ -4314,36 +4208,35 @@
 	|| INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
 	|| INTVAL (operands[2]) == 31
 	|| (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
-  "*
 {
   operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
   if (INTVAL (operands[2]) == 63)
-    return \"add%.l %0,%0\;subx%.l %0,%0\;move%.l %0,%1\";
+    return "add%.l %0,%0\;subx%.l %0,%0\;move%.l %0,%1";
   CC_STATUS_INIT;
   if (INTVAL (operands[2]) == 1)
-    return \"asr%.l %#1,%0\;roxr%.l %#1,%1\";
+    return "asr%.l %#1,%0\;roxr%.l %#1,%1";
   else if (INTVAL (operands[2]) == 8)
-    return \"move%.b %0,%1\;asr%.l %#8,%0\;ror%.l %#8,%1\";
+    return "move%.b %0,%1\;asr%.l %#8,%0\;ror%.l %#8,%1";
   else if (INTVAL (operands[2]) == 16)
-    return \"move%.w %0,%1\;swap %0\;ext%.l %0\;swap %1\";
+    return "move%.w %0,%1\;swap %0\;ext%.l %0\;swap %1";
   else if (INTVAL (operands[2]) == 48)
-    return \"swap %0\;ext%.l %0\;move%.l %0,%1\;smi %0\;ext%.w %0\";
+    return "swap %0\;ext%.l %0\;move%.l %0,%1\;smi %0\;ext%.w %0";
   else if (INTVAL (operands[2]) == 31)
-    return \"add%.l %1,%1\;addx%.l %0,%0\;move%.l %0,%1\;subx%.l %0,%0\";
+    return "add%.l %1,%1\;addx%.l %0,%0\;move%.l %0,%1\;subx%.l %0,%0";
   else if (INTVAL (operands[2]) == 2)
-    return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
+    return "asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1";
   else if (INTVAL (operands[2]) == 3)
-    return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
+    return "asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1";
   else /* 32 < INTVAL (operands[2]) <= 63 */
     {
       operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
-      output_asm_insn (INTVAL (operands[2]) <= 8 ? \"asr%.l %2,%0\" :
-			\"moveq %2,%1\;asr%.l %1,%0\", operands);
-      output_asm_insn (\"mov%.l %0,%1\;smi %0\", operands);
-      return INTVAL (operands[2]) >= 15 ? \"ext%.w %d0\" :
-	     TARGET_68020 ? \"extb%.l %0\" : \"ext%.w %0\;ext%.l %0\";
+      output_asm_insn (INTVAL (operands[2]) <= 8 ? "asr%.l %2,%0" :
+			"moveq %2,%1\;asr%.l %1,%0", operands);
+      output_asm_insn ("mov%.l %0,%1\;smi %0", operands);
+      return INTVAL (operands[2]) >= 15 ? "ext%.w %d0" :
+	     TARGET_68020 ? "extb%.l %0" : "ext%.w %0\;ext%.l %0";
     }
-} ")
+})
 
 (define_expand "ashrdi3"
   [(set (match_operand:DI 0 "nonimmediate_operand" "")
@@ -4368,10 +4261,9 @@
 	(ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
 		     (const_int 31)))]
   ""
-  "*
 {
-  return \"add%.l %0,%0\;subx%.l %0,%0\";
-}")
+  return "add%.l %0,%0\;subx%.l %0,%0";
+})
 
 (define_insn "ashrsi3"
   [(set (match_operand:SI 0 "register_operand" "=d")
@@ -4419,10 +4311,9 @@
 ;;            (subreg:SI (lshiftrt:DI (match_dup 0)
 ;;                    (const_int 32)) 4))]
 ;;  ""
-;;  "*
 ;;{
-;;  return \"move%.l %0,%1\";
-;;} ")
+;;  return "move%.l %0,%1";
+;;})
 ;;
 ;;(define_insn ""
 ;;        [(set (cc0)
@@ -4432,37 +4323,34 @@
 ;;            (lshiftrt:DI (match_dup 0)
 ;;                (const_int 32)))]
 ;;  ""
-;;  "*
 ;;{
 ;;  if (GET_CODE (operands[1]) == REG)
 ;;    operands[2] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
 ;;  else
 ;;    operands[2] = adjust_address (operands[1], SImode, 4);
-;;  return \"move%.l %0,%2\;clr%.l %1\";
-;;} ")
+;;  return "move%.l %0,%2\;clr%.l %1";
+;;})
 
 (define_insn "subreg1lshrdi_const32"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
     (subreg:SI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
             (const_int 32)) 4))]
   ""
-  "*
 {
-  return \"move%.l %1,%0\";
-} ")
+  return "move%.l %1,%0";
+})
 
 (define_insn "lshrdi_const32"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=ro,<,>")
 	(lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro,ro")
 		     (const_int 32)))]
   ""
-  "*
 {
   CC_STATUS_INIT;
   if (which_alternative == 1)
-    return \"move%.l %1,%0\;clr%.l %0\";
+    return "move%.l %1,%0\;clr%.l %0";
   if (which_alternative == 2)
-    return \"clr%.l %0\;move%.l %1,%0\";
+    return "clr%.l %0\;move%.l %1,%0";
   if (GET_CODE (operands[0]) == REG)
     operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
   else
@@ -4472,10 +4360,10 @@
   else
     operands[3] = adjust_address (operands[1], SImode, 4);
   if (ADDRESS_REG_P (operands[0]))
-    return \"move%.l %1,%2\;sub%.l %0,%0\";
+    return "move%.l %1,%2\;sub%.l %0,%0";
   else
-    return \"move%.l %1,%2\;clr%.l %0\";
-} ")
+    return "move%.l %1,%2\;clr%.l %0";
+})
 
 ;; The predicate below must be general_operand, because lshrdi3 allows that
 (define_insn "lshrdi_const"
@@ -4486,39 +4374,37 @@
     && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
 	 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
 	 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
-  "*
 {
   operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
   if (INTVAL (operands[2]) == 63)
-    return \"add%.l %0,%0\;clr%.l %0\;clr%.l %1\;addx%.l %1,%1\";
+    return "add%.l %0,%0\;clr%.l %0\;clr%.l %1\;addx%.l %1,%1";
   CC_STATUS_INIT;
   if (INTVAL (operands[2]) == 1)
-    return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\";
+    return "lsr%.l %#1,%0\;roxr%.l %#1,%1";
   else if (INTVAL (operands[2]) == 8)
-    return \"move%.b %0,%1\;lsr%.l %#8,%0\;ror%.l %#8,%1\";
+    return "move%.b %0,%1\;lsr%.l %#8,%0\;ror%.l %#8,%1";
   else if (INTVAL (operands[2]) == 16)
-    return \"move%.w %0,%1\;clr%.w %0\;swap %1\;swap %0\";
+    return "move%.w %0,%1\;clr%.w %0\;swap %1\;swap %0";
   else if (INTVAL (operands[2]) == 48)
-    return \"move%.l %0,%1\;clr%.w %1\;clr%.l %0\;swap %1\";
+    return "move%.l %0,%1\;clr%.w %1\;clr%.l %0\;swap %1";
   else if (INTVAL (operands[2]) == 2)
-    return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
+    return "lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1";
   else if (INTVAL (operands[2]) == 3)
-    return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
+    return "lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1";
   else /* 32 < INTVAL (operands[2]) <= 63 */
     {
       operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
-      output_asm_insn (INTVAL (operands[2]) <= 8 ? \"lsr%.l %2,%0\" :
-			\"moveq %2,%1\;lsr%.l %1,%0\", operands);
-      return \"mov%.l %0,%1\;moveq %#0,%0\";
+      output_asm_insn (INTVAL (operands[2]) <= 8 ? "lsr%.l %2,%0" :
+			"moveq %2,%1\;lsr%.l %1,%0", operands);
+      return "mov%.l %0,%1\;moveq %#0,%0";
     }
-} ")
+})
 
 (define_expand "lshrdi3"
   [(set (match_operand:DI 0 "nonimmediate_operand" "")
 	(lshiftrt:DI (match_operand:DI 1 "general_operand" "")
 		     (match_operand 2 "const_int_operand" "")))]
   "!TARGET_COLDFIRE"
-  "
 {
   /* ???  This is a named pattern like this is not allowed to FAIL based
      on its operands.  */
@@ -4527,7 +4413,7 @@
 	  && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
 	  && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
     FAIL;
-} ")
+})
 
 ;; On all 68k models, this makes faster code in a special case.
 
@@ -4536,10 +4422,9 @@
 	(lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
 		     (const_int 31)))]
   ""
-  "*
 {
-  return \"add%.l %0,%0\;subx%.l %0,%0\;neg%.l %0\";
-}")
+  return "add%.l %0,%0\;subx%.l %0,%0\;neg%.l %0";
+})
 
 ;; On most 68k models, this makes faster code in a special case.
 
@@ -4548,11 +4433,10 @@
 	(lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
 		     (const_int 16)))]
   "!TARGET_68060"
-  "*
 {
   CC_STATUS_INIT;
-  return \"clr%.w %0\;swap %0\";
-}")
+  return "clr%.w %0\;swap %0";
+})
 
 ;; On the 68000, this makes faster code in a special case.
 
@@ -4562,12 +4446,11 @@
 		     (match_operand:SI 2 "const_int_operand" "n")))]
   "(! TARGET_68020 && !TARGET_COLDFIRE
     && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
-  "*
 {
   /* I think lsr%.w sets the CC properly.  */
   operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
-  return \"clr%.w %0\;swap %0\;lsr%.w %2,%0\";
-}")
+  return "clr%.w %0\;swap %0\;lsr%.w %2,%0";
+})
 
 (define_insn "lshrsi3"
   [(set (match_operand:SI 0 "register_operand" "=d")
@@ -4611,82 +4494,77 @@
 	(rotate:SI (match_operand:SI 1 "register_operand" "0")
 		   (match_operand:SI 2 "general_operand" "dINO")))]
   "!TARGET_COLDFIRE"
-  "*
 {
   if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)
-    return \"swap %0\";
+    return "swap %0";
   else if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 16)
     {
       operands[2] = GEN_INT (32 - INTVAL (operands[2]));
-      return \"ror%.l %2,%0\";
+      return "ror%.l %2,%0";
     }
   else
-    return \"rol%.l %2,%0\";
-}")
+    return "rol%.l %2,%0";
+})
 
 (define_insn "rotlhi3"
   [(set (match_operand:HI 0 "register_operand" "=d")
 	(rotate:HI (match_operand:HI 1 "register_operand" "0")
 		   (match_operand:HI 2 "general_operand" "dIP")))]
   "!TARGET_COLDFIRE"
-  "*
 {
   if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
     {
       operands[2] = GEN_INT (16 - INTVAL (operands[2]));
-      return \"ror%.w %2,%0\";
+      return "ror%.w %2,%0";
     }
   else
-    return \"rol%.w %2,%0\";
-}")
+    return "rol%.w %2,%0";
+})
 
 (define_insn ""
   [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
 	(rotate:HI (match_dup 0)
 		   (match_operand:HI 1 "general_operand" "dIP")))]
   "!TARGET_COLDFIRE"
-  "*
 {
   if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
     {
       operands[2] = GEN_INT (16 - INTVAL (operands[2]));
-      return \"ror%.w %2,%0\";
+      return "ror%.w %2,%0";
     }
   else
-    return \"rol%.w %2,%0\";
-}")
+    return "rol%.w %2,%0";
+})
 
 (define_insn "rotlqi3"
   [(set (match_operand:QI 0 "register_operand" "=d")
 	(rotate:QI (match_operand:QI 1 "register_operand" "0")
 		   (match_operand:QI 2 "general_operand" "dI")))]
   "!TARGET_COLDFIRE"
-  "*
 {
   if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
     {
       operands[2] = GEN_INT (8 - INTVAL (operands[2]));
-      return \"ror%.b %2,%0\";
+      return "ror%.b %2,%0";
     }
   else
-    return \"rol%.b %2,%0\";
-}")
+    return "rol%.b %2,%0";
+})
 
 (define_insn ""
   [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
 	(rotate:QI (match_dup 0)
 		   (match_operand:QI 1 "general_operand" "dI")))]
   "!TARGET_COLDFIRE"
-  "*
 {
   if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
     {
       operands[2] = GEN_INT (8 - INTVAL (operands[2]));
-      return \"ror%.b %2,%0\";
+      return "ror%.b %2,%0";
     }
   else
-    return \"rol%.b %2,%0\";
-}")
+    return "rol%.b %2,%0";
+})
 
 (define_insn "rotrsi3"
   [(set (match_operand:SI 0 "register_operand" "=d")
@@ -4733,11 +4611,10 @@
 		(match_operand:SI 1 "general_operand" "d")) 3)
 	(match_dup 0)))]
   ""
-  "*
 {
   CC_STATUS_INIT;
-  return \"bset %1,%0\";
-}")
+  return "bset %1,%0";
+})
 
 ;; set bit, bit number is (sign/zero)_extended from HImode/QImode
 (define_insn ""
@@ -4747,11 +4624,10 @@
 		[(match_operand 1 "general_operand" "d")])) 3)
 	(match_dup 0)))]
   ""
-  "*
 {
   CC_STATUS_INIT;
-  return \"bset %1,%0\";
-}")
+  return "bset %1,%0";
+})
 
 ;; clear bit, bit number is int
 (define_insn "bclrmemqi"
@@ -4761,11 +4637,10 @@
 	    (match_operand:SI 1 "general_operand" "d")))
     (const_int 0))]
   ""
-  "*
 {
   CC_STATUS_INIT;
-  return \"bclr %1,%0\";
-}")
+  return "bclr %1,%0";
+})
 
 ;; clear bit, bit number is (sign/zero)_extended from HImode/QImode
 (define_insn ""
@@ -4776,11 +4651,10 @@
 		[(match_operand 1 "general_operand" "d")])))
     (const_int 0))]
   ""
-  "*
 {
   CC_STATUS_INIT;
-  return \"bclr %1,%0\";
-}")
+  return "bclr %1,%0";
+})
 
 ;; Special cases of bit-field insns which we should
 ;; recognize in preference to the general case.
@@ -4802,13 +4676,12 @@
   "TARGET_68020 && TARGET_BITFIELD
    && (INTVAL (operands[1]) % 8) == 0
    && ! mode_dependent_address_p (XEXP (operands[0], 0))"
-  "*
 {
   operands[0]
     = adjust_address (operands[0], SImode, INTVAL (operands[1]) / 8);
 
-  return \"move%.l %2,%0\";
-}")
+  return "move%.l %2,%0";
+})
 
 (define_insn ""
   [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+do")
@@ -4820,12 +4693,11 @@
    && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
    && (GET_CODE (operands[0]) == REG
        || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
-  "*
 {
   if (REG_P (operands[0]))
     {
       if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32)
-        return \"bfins %3,%0{%b2:%b1}\";
+        return "bfins %3,%0{%b2:%b1}";
     }
   else
     operands[0] = adjust_address (operands[0],
@@ -4838,9 +4710,9 @@
 				  (32 - INTVAL (operands[1])) / 8);
 
   if (INTVAL (operands[1]) == 8)
-    return \"move%.b %3,%0\";
-  return \"move%.w %3,%0\";
-}")
+    return "move%.b %3,%0";
+  return "move%.w %3,%0";
+})
 
 
 ;
@@ -4858,13 +4730,12 @@
   "TARGET_68020 && TARGET_BITFIELD
    && (INTVAL (operands[2]) % 8) == 0
    && ! mode_dependent_address_p (XEXP (operands[1], 0))"
-  "*
 {
   operands[1]
     = adjust_address (operands[1], SImode, INTVAL (operands[2]) / 8);
 
-  return \"move%.l %1,%0\";
-}")
+  return "move%.l %1,%0";
+})
 
 (define_insn ""
   [(set (match_operand:SI 0 "nonimmediate_operand" "=&d")
@@ -4876,28 +4747,27 @@
    && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
    && (GET_CODE (operands[1]) == REG
        || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
-  "*
 {
   cc_status.flags |= CC_NOT_NEGATIVE;
   if (REG_P (operands[1]))
     {
       if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
-	return \"bfextu %1{%b3:%b2},%0\";
+	return "bfextu %1{%b3:%b2},%0";
     }
   else
     operands[1]
       = adjust_address (operands[1], SImode, INTVAL (operands[3]) / 8);
 
-  output_asm_insn (\"clr%.l %0\", operands);
+  output_asm_insn ("clr%.l %0", operands);
   if (GET_CODE (operands[0]) == MEM)
     operands[0] = adjust_address (operands[0],
 				  INTVAL (operands[2]) == 8 ? QImode : HImode,
 				  (32 - INTVAL (operands[1])) / 8);
 
   if (INTVAL (operands[2]) == 8)
-    return \"move%.b %1,%0\";
-  return \"move%.w %1,%0\";
-}")
+    return "move%.b %1,%0";
+  return "move%.w %1,%0";
+})
 
 ;
 ; Special case for 32-bit field in memory.  This only occurs when 32-bit
@@ -4914,13 +4784,12 @@
   "TARGET_68020 && TARGET_BITFIELD
    && (INTVAL (operands[2]) % 8) == 0
    && ! mode_dependent_address_p (XEXP (operands[1], 0))"
-  "*
 {
   operands[1]
     = adjust_address (operands[1], SImode, INTVAL (operands[2]) / 8);
 
-  return \"move%.l %1,%0\";
-}")
+  return "move%.l %1,%0";
+})
 
 (define_insn ""
   [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
@@ -4932,12 +4801,11 @@
    && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
    && (GET_CODE (operands[1]) == REG
        || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
-  "*
 {
   if (REG_P (operands[1]))
     {
       if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
-	return \"bfexts %1{%b3:%b2},%0\";
+	return "bfexts %1{%b3:%b2},%0";
     }
   else
     operands[1]
@@ -4946,9 +4814,9 @@
 			INTVAL (operands[3]) / 8);
 
   if (INTVAL (operands[2]) == 8)
-    return \"move%.b %1,%0\;extb%.l %0\";
-  return \"move%.w %1,%0\;ext%.l %0\";
-}")
+    return "move%.b %1,%0\;extb%.l %0";
+  return "move%.w %1,%0\;ext%.l %0";
+})
 
 ;; Bit-field instructions, general cases.
 ;; "o,d" constraint causes a nonoffsettable memref to match the "o"
@@ -4984,7 +4852,6 @@
 			 (match_operand:SI 2 "general_operand" "di,di")
 			 (match_operand:SI 3 "general_operand" "di,di")))]
   "TARGET_68020 && TARGET_BITFIELD"
-  "*
 {
   if (GET_CODE (operands[2]) == CONST_INT)
     {
@@ -4995,8 +4862,8 @@
     {
       CC_STATUS_INIT;
     }
-  return \"bfextu %1{%b3:%b2},%0\";
-}")
+  return "bfextu %1{%b3:%b2},%0";
+})
 
 (define_insn ""
   [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
@@ -5008,11 +4875,10 @@
    && (INTVAL (operands[3]) == -1
        || (GET_CODE (operands[1]) == CONST_INT
            && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))"
-  "*
 {
   CC_STATUS_INIT;
-  return \"bfchg %0{%b2:%b1}\";
-}")
+  return "bfchg %0{%b2:%b1}";
+})
 
 (define_insn ""
   [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
@@ -5020,11 +4886,10 @@
 			 (match_operand:SI 2 "general_operand" "di"))
 	(const_int 0))]
   "TARGET_68020 && TARGET_BITFIELD"
-  "*
 {
   CC_STATUS_INIT;
-  return \"bfclr %0{%b2:%b1}\";
-}")
+  return "bfclr %0{%b2:%b1}";
+})
 
 (define_insn ""
   [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
@@ -5032,11 +4897,10 @@
 			 (match_operand:SI 2 "general_operand" "di"))
 	(const_int -1))]
   "TARGET_68020 && TARGET_BITFIELD"
-  "*
 {
   CC_STATUS_INIT;
-  return \"bfset %0{%b2:%b1}\";
-}")
+  return "bfset %0{%b2:%b1}";
+})
 
 (define_expand "insv"
   [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "")
@@ -5071,7 +4935,6 @@
 			 (match_operand:SI 2 "general_operand" "di")
 			 (match_operand:SI 3 "general_operand" "di")))]
   "TARGET_68020 && TARGET_BITFIELD"
-  "*
 {
   if (GET_CODE (operands[2]) == CONST_INT)
     {
@@ -5082,8 +4945,8 @@
     {
       CC_STATUS_INIT;
     }
-  return \"bfextu %1{%b3:%b2},%0\";
-}")
+  return "bfextu %1{%b3:%b2},%0";
+})
 
 (define_insn ""
   [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
@@ -5091,11 +4954,10 @@
 			 (match_operand:SI 2 "general_operand" "di"))
 	(const_int 0))]
   "TARGET_68020 && TARGET_BITFIELD"
-  "*
 {
   CC_STATUS_INIT;
-  return \"bfclr %0{%b2:%b1}\";
-}")
+  return "bfclr %0{%b2:%b1}";
+})
 
 (define_insn ""
   [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
@@ -5103,11 +4965,10 @@
 			 (match_operand:SI 2 "general_operand" "di"))
 	(const_int -1))]
   "TARGET_68020 && TARGET_BITFIELD"
-  "*
 {
   CC_STATUS_INIT;
-  return \"bfset %0{%b2:%b1}\";
-}")
+  return "bfset %0{%b2:%b1}";
+})
 
 (define_insn ""
   [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
@@ -5115,19 +4976,18 @@
 			 (match_operand:SI 2 "general_operand" "di"))
 	(match_operand:SI 3 "register_operand" "d"))]
   "TARGET_68020 && TARGET_BITFIELD"
-  "*
 {
 #if 0
   /* These special cases are now recognized by a specific pattern.  */
   if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
       && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16)
-    return \"move%.w %3,%0\";
+    return "move%.w %3,%0";
   if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
       && INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8)
-    return \"move%.b %3,%0\";
+    return "move%.b %3,%0";
 #endif
-  return \"bfins %3,%0{%b2:%b1}\";
-}")
+  return "bfins %3,%0{%b2:%b1}";
+})
 
 ;; Special patterns for optimizing bit-field instructions.
 
@@ -5137,7 +4997,6 @@
 			 (match_operand:SI 1 "const_int_operand" "n")
 			 (match_operand:SI 2 "general_operand" "di")))]
   "TARGET_68020 && TARGET_BITFIELD"
-  "*
 {
   if (operands[1] == const1_rtx
       && GET_CODE (operands[2]) == CONST_INT)
@@ -5152,8 +5011,8 @@
     }
   if (INTVAL (operands[1]) != 32)
     cc_status.flags = CC_NOT_NEGATIVE;
-  return \"bftst %0{%b2:%b1}\";
-}")
+  return "bftst %0{%b2:%b1}";
+})
 
 
 ;;; now handle the register cases
@@ -5163,7 +5022,6 @@
 			 (match_operand:SI 1 "const_int_operand" "n")
 			 (match_operand:SI 2 "general_operand" "di")))]
   "TARGET_68020 && TARGET_BITFIELD"
-  "*
 {
   if (operands[1] == const1_rtx
       && GET_CODE (operands[2]) == CONST_INT)
@@ -5177,28 +5035,26 @@
     }
   if (INTVAL (operands[1]) != 32)
     cc_status.flags = CC_NOT_NEGATIVE;
-  return \"bftst %0{%b2:%b1}\";
-}")
+  return "bftst %0{%b2:%b1}";
+})
 
 (define_insn "scc0_di"
   [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
     (match_operator 1 "valid_dbcc_comparison_p"
       [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
   "! TARGET_COLDFIRE"
-  "*
 {
   return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
-} ")
+})
 
 (define_insn "scc0_di_5200"
   [(set (match_operand:QI 0 "nonimmediate_operand" "=d")
     (match_operator 1 "valid_dbcc_comparison_p"
       [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
   "TARGET_COLDFIRE"
-  "*
 {
   return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
-} ")
+})
 
 (define_insn "scc_di"
   [(set (match_operand:QI 0 "nonimmediate_operand" "=dm,dm")
@@ -5206,10 +5062,9 @@
       [(match_operand:DI 2 "general_operand" "ro,r")
        (match_operand:DI 3 "general_operand" "r,ro")]))]
   "! TARGET_COLDFIRE"
-  "*
 {
   return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
-} ")
+})
 
 (define_insn "scc_di_5200"
   [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d")
@@ -5217,10 +5072,9 @@
       [(match_operand:DI 2 "general_operand" "ro,r")
        (match_operand:DI 3 "general_operand" "r,ro")]))]
   "TARGET_COLDFIRE"
-  "*
 {
   return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
-} ")
+})
 
 ;; Note that operand 0 of an SCC insn is supported in the hardware as
 ;; memory, but we cannot allow it to be in memory in case the address
@@ -5243,10 +5097,10 @@
   [(set (match_operand:QI 0 "register_operand" "=d")
 	(eq:QI (cc0) (const_int 0)))]
   ""
-  "*
+{
   cc_status = cc_prev_status;
-  OUTPUT_JUMP (\"seq %0\", \"fseq %0\", \"seq %0\");
-")
+  OUTPUT_JUMP ("seq %0", "fseq %0", "seq %0");
+})
 
 (define_expand "sne"
   [(set (match_operand:QI 0 "register_operand" "")
@@ -5265,10 +5119,10 @@
   [(set (match_operand:QI 0 "register_operand" "=d")
 	(ne:QI (cc0) (const_int 0)))]
   ""
-  "*
+{
   cc_status = cc_prev_status;
-  OUTPUT_JUMP (\"sne %0\", \"fsne %0\", \"sne %0\");
-")
+  OUTPUT_JUMP ("sne %0", "fsne %0", "sne %0");
+})
 
 (define_expand "sgt"
   [(set (match_operand:QI 0 "register_operand" "")
@@ -5287,10 +5141,10 @@
   [(set (match_operand:QI 0 "register_operand" "=d")
 	(gt:QI (cc0) (const_int 0)))]
   ""
-  "*
+{
   cc_status = cc_prev_status;
-  OUTPUT_JUMP (\"sgt %0\", \"fsgt %0\", 0);
-")
+  OUTPUT_JUMP ("sgt %0", "fsgt %0", 0);
+})
 
 (define_expand "sgtu"
   [(set (match_operand:QI 0 "register_operand" "")
@@ -5302,9 +5156,10 @@
   [(set (match_operand:QI 0 "register_operand" "=d")
 	(gtu:QI (cc0) (const_int 0)))]
   ""
-  "*
-   cc_status = cc_prev_status;
-   return \"shi %0\"; ")
+{
+  cc_status = cc_prev_status;
+  return "shi %0";
+})
 
 (define_expand "slt"
   [(set (match_operand:QI 0 "register_operand" "")
@@ -5323,9 +5178,10 @@
   [(set (match_operand:QI 0 "register_operand" "=d")
 	(lt:QI (cc0) (const_int 0)))]
   ""
-  "*
+{
    cc_status = cc_prev_status;
-   OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ")
+   OUTPUT_JUMP ("slt %0", "fslt %0", "smi %0");
+})
 
 (define_expand "sltu"
   [(set (match_operand:QI 0 "register_operand" "")
@@ -5337,9 +5193,10 @@
   [(set (match_operand:QI 0 "register_operand" "=d")
 	(ltu:QI (cc0) (const_int 0)))]
   ""
-  "*
+{
    cc_status = cc_prev_status;
-   return \"scs %0\"; ")
+   return "scs %0";
+})
 
 (define_expand "sge"
   [(set (match_operand:QI 0 "register_operand" "")
@@ -5358,9 +5215,10 @@
   [(set (match_operand:QI 0 "register_operand" "=d")
 	(ge:QI (cc0) (const_int 0)))]
   ""
-  "*
+{
    cc_status = cc_prev_status;
-   OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ")
+   OUTPUT_JUMP ("sge %0", "fsge %0", "spl %0");
+})
 
 (define_expand "sgeu"
   [(set (match_operand:QI 0 "register_operand" "")
@@ -5372,9 +5230,10 @@
   [(set (match_operand:QI 0 "register_operand" "=d")
 	(geu:QI (cc0) (const_int 0)))]
   ""
-  "*
+{
    cc_status = cc_prev_status;
-   return \"scc %0\"; ")
+   return "scc %0";
+})
 
 (define_expand "sle"
   [(set (match_operand:QI 0 "register_operand" "")
@@ -5393,10 +5252,10 @@
   [(set (match_operand:QI 0 "register_operand" "=d")
 	(le:QI (cc0) (const_int 0)))]
   ""
-  "*
+{
   cc_status = cc_prev_status;
-  OUTPUT_JUMP (\"sle %0\", \"fsle %0\", 0);
-")
+  OUTPUT_JUMP ("sle %0", "fsle %0", 0);
+})
 
 (define_expand "sleu"
   [(set (match_operand:QI 0 "register_operand" "")
@@ -5408,9 +5267,10 @@
   [(set (match_operand:QI 0 "register_operand" "=d")
 	(leu:QI (cc0) (const_int 0)))]
   ""
-  "*
+{
    cc_status = cc_prev_status;
-   return \"sls %0\"; ")
+   return "sls %0";
+})
 
 (define_expand "sordered"
   [(set (match_operand:QI 0 "register_operand" "")
@@ -5610,15 +5470,14 @@
         (pc)))
    (clobber (match_scratch:SI 2 "=d,d"))]
   ""
-  "*
 {
   CC_STATUS_INIT;
   if (which_alternative == 1)
     {
       if (MOTOROLA)
-	return \"move%.l %0,%2\;or%.l %0,%2\;jbeq %l1\";
+	return "move%.l %0,%2\;or%.l %0,%2\;jbeq %l1";
       else
-	return \"move%.l %0,%2\;or%.l %0,%2\;jeq %l1\";
+	return "move%.l %0,%2\;or%.l %0,%2\;jeq %l1";
     }
   if ((cc_prev_status.value1
       && rtx_equal_p (cc_prev_status.value1, operands[0]))
@@ -5626,7 +5485,7 @@
       && rtx_equal_p (cc_prev_status.value2, operands[0])))
     {
       cc_status = cc_prev_status;
-      return MOTOROLA ? \"jbeq %l1\" : \"jeq %l1\";
+      return MOTOROLA ? "jbeq %l1" : "jeq %l1";
     }
   if (GET_CODE (operands[0]) == REG)
     operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
@@ -5639,46 +5498,46 @@
 	  if (reg_overlap_mentioned_p (operands[2], operands[3]))
 	    {
 	      if (MOTOROLA)
-		return \"or%.l %0,%2\;jbeq %l1\";
+		return "or%.l %0,%2\;jbeq %l1";
 	      else
-		return \"or%.l %0,%2\;jeq %l1\";
+		return "or%.l %0,%2\;jeq %l1";
 	    }
 	  else
 	    {
 	      if (MOTOROLA)
-		return \"or%.l %3,%2\;jbeq %l1\";
+		return "or%.l %3,%2\;jbeq %l1";
 	      else
-		return \"or%.l %3,%2\;jeq %l1\";
+		return "or%.l %3,%2\;jeq %l1";
 	    }
 	}
       if (MOTOROLA)
-	return \"move%.l %0,%2\;or%.l %3,%2\;jbeq %l1\";
+	return "move%.l %0,%2\;or%.l %3,%2\;jbeq %l1";
       else
-	return \"move%.l %0,%2\;or%.l %3,%2\;jeq %l1\";
+	return "move%.l %0,%2\;or%.l %3,%2\;jeq %l1";
     }
   operands[4] = gen_label_rtx();
   if (TARGET_68020 || TARGET_COLDFIRE)
     {
       if (MOTOROLA)
-	output_asm_insn (\"tst%.l %0\;jbne %l4\;tst%.l %3\;jbeq %l1\", operands);
+	output_asm_insn ("tst%.l %0\;jbne %l4\;tst%.l %3\;jbeq %l1", operands);
       else
-	output_asm_insn (\"tst%.l %0\;jne %l4\;tst%.l %3\;jeq %l1\", operands);
+	output_asm_insn ("tst%.l %0\;jne %l4\;tst%.l %3\;jeq %l1", operands);
     }
   else
     {
       if (MOTOROLA)
 #ifdef SGS_CMP_ORDER
-	output_asm_insn (\"cmp%.w %0,%#0\;jbne %l4\;cmp%.w %3,%#0\;jbeq %l1\", operands);
+	output_asm_insn ("cmp%.w %0,%#0\;jbne %l4\;cmp%.w %3,%#0\;jbeq %l1", operands);
 #else
-	output_asm_insn (\"cmp%.w %#0,%0\;jbne %l4\;cmp%.w %#0,%3\;jbeq %l1\", operands);
+	output_asm_insn ("cmp%.w %#0,%0\;jbne %l4\;cmp%.w %#0,%3\;jbeq %l1", operands);
 #endif
       else
-	output_asm_insn (\"cmp%.w %#0,%0\;jne %l4\;cmp%.w %#0,%3\;jeq %l1\", operands);
+	output_asm_insn ("cmp%.w %#0,%0\;jne %l4\;cmp%.w %#0,%3\;jeq %l1", operands);
     }
-  (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
+  (*targetm.asm_out.internal_label) (asm_out_file, "L",
 				CODE_LABEL_NUMBER (operands[4]));
-  return \"\";
-} ")
+  return "";
+})
 
 (define_insn "bne0_di"
   [(set (pc)
@@ -5688,7 +5547,6 @@
         (pc)))
    (clobber (match_scratch:SI 2 "=d,X"))]
   ""
-  "*
 {
   if ((cc_prev_status.value1
       && rtx_equal_p (cc_prev_status.value1, operands[0]))
@@ -5696,7 +5554,7 @@
       && rtx_equal_p (cc_prev_status.value2, operands[0])))
     {
       cc_status = cc_prev_status;
-      return MOTOROLA ? \"jbne %l1\" : \"jne %l1\";
+      return MOTOROLA ? "jbne %l1" : "jne %l1";
     }
   CC_STATUS_INIT;
   if (GET_CODE (operands[0]) == REG)
@@ -5710,42 +5568,42 @@
 	  if (reg_overlap_mentioned_p (operands[2], operands[3]))
 	    {
 	      if (MOTOROLA)
-		return \"or%.l %0,%2\;jbne %l1\";
+		return "or%.l %0,%2\;jbne %l1";
 	      else
-		return \"or%.l %0,%2\;jne %l1\";
+		return "or%.l %0,%2\;jne %l1";
 	    }
 	  else
 	    {
 	      if (MOTOROLA)
-		return \"or%.l %3,%2\;jbne %l1\";
+		return "or%.l %3,%2\;jbne %l1";
 	      else
-		return \"or%.l %3,%2\;jne %l1\";
+		return "or%.l %3,%2\;jne %l1";
 	    }
 	}
       if (MOTOROLA)
-	return \"move%.l %0,%2\;or%.l %3,%2\;jbne %l1\";
+	return "move%.l %0,%2\;or%.l %3,%2\;jbne %l1";
       else
-	return \"move%.l %0,%2\;or%.l %3,%2\;jne %l1\";
+	return "move%.l %0,%2\;or%.l %3,%2\;jne %l1";
     }
   if (TARGET_68020 || TARGET_COLDFIRE)
     {
       if (MOTOROLA)
-	return \"tst%.l %0\;jbne %l1\;tst%.l %3\;jbne %l1\";
+	return "tst%.l %0\;jbne %l1\;tst%.l %3\;jbne %l1";
       else
-	return \"tst%.l %0\;jne %l1\;tst%.l %3\;jne %l1\";
+	return "tst%.l %0\;jne %l1\;tst%.l %3\;jne %l1";
     }
   else
     {
       if (MOTOROLA)
 #ifdef SGS_CMP_ORDER
-	return \"cmp%.w %0,%#0\;jbne %l1\;cmp%.w %3,%#0\;jbne %l1\";
+	return "cmp%.w %0,%#0\;jbne %l1\;cmp%.w %3,%#0\;jbne %l1";
 #else
-	return \"cmp%.w %#0,%0\;jbne %l1\;cmp%.w %#0,%3\;jbne %l1\";
+	return "cmp%.w %#0,%0\;jbne %l1\;cmp%.w %#0,%3\;jbne %l1";
 #endif
       else
-	return \"cmp%.w %#0,%0\;jne %l1\;cmp%.w %#0,%3\;jne %l1\";
+	return "cmp%.w %#0,%0\;jne %l1\;cmp%.w %#0,%3\;jne %l1";
     }
-} ")
+})
 
 (define_insn "bge0_di"
   [(set (pc)
@@ -5754,7 +5612,6 @@
         (label_ref (match_operand 1 "" ""))
         (pc)))]
   ""
-  "*
 {
   if ((cc_prev_status.value1
       && rtx_equal_p (cc_prev_status.value1, operands[0]))
@@ -5764,28 +5621,28 @@
       cc_status = cc_prev_status;
       if (cc_status.flags & CC_REVERSED)
 	{
-	  return MOTOROLA ? \"jble %l1\" : \"jle %l1\";
+	  return MOTOROLA ? "jble %l1" : "jle %l1";
 	}
       else
 	{
-	  return MOTOROLA ? \"jbpl %l1\" : \"jpl %l1\";
+	  return MOTOROLA ? "jbpl %l1" : "jpl %l1";
 	}
     }
   CC_STATUS_INIT;
   if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0]))
-    output_asm_insn(\"tst%.l %0\", operands);
+    output_asm_insn("tst%.l %0", operands);
   else
     {
       /* On an address reg, cmpw may replace cmpl.  */
 #ifdef SGS_CMP_ORDER
-      output_asm_insn(\"cmp%.w %0,%#0\", operands);
+      output_asm_insn("cmp%.w %0,%#0", operands);
 #else
-      output_asm_insn(\"cmp%.w %#0,%0\", operands);
+      output_asm_insn("cmp%.w %#0,%0", operands);
 #endif
     }
 
-  return MOTOROLA ? \"jbpl %l1\" : \"jpl %l1\";
-} ")
+  return MOTOROLA ? "jbpl %l1" : "jpl %l1";
+})
 
 (define_insn "blt0_di"
   [(set (pc)
@@ -5794,7 +5651,6 @@
         (label_ref (match_operand 1 "" ""))
         (pc)))]
   ""
-  "*
 {
   if ((cc_prev_status.value1
       && rtx_equal_p (cc_prev_status.value1, operands[0]))
@@ -5804,28 +5660,28 @@
       cc_status = cc_prev_status;
       if (cc_status.flags & CC_REVERSED)
 	{
-	  return MOTOROLA ? \"jbgt %l1\" : \"jgt %l1\";
+	  return MOTOROLA ? "jbgt %l1" : "jgt %l1";
 	}
       else
 	{
-	  return MOTOROLA ? \"jbmi %l1\" : \"jmi %l1\";
+	  return MOTOROLA ? "jbmi %l1" : "jmi %l1";
 	}
     }
   CC_STATUS_INIT;
   if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0]))
-    output_asm_insn(\"tst%.l %0\", operands);
+    output_asm_insn("tst%.l %0", operands);
   else
     {
       /* On an address reg, cmpw may replace cmpl.  */
 #ifdef SGS_CMP_ORDER
-      output_asm_insn(\"cmp%.w %0,%#0\", operands);
+      output_asm_insn("cmp%.w %0,%#0", operands);
 #else
-      output_asm_insn(\"cmp%.w %#0,%0\", operands);
+      output_asm_insn("cmp%.w %#0,%0", operands);
 #endif
     }
 
-  return MOTOROLA ? \"jbmi %l1\" : \"jmi %l1\";
-} ")
+  return MOTOROLA ? "jbmi %l1" : "jmi %l1";
+})
 
 (define_insn "beq"
   [(set (pc)
@@ -5834,13 +5690,12 @@
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "*
 {
   if (MOTOROLA)
-    OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
+    OUTPUT_JUMP ("jbeq %l0", "fbeq %l0", "jbeq %l0");
   else
-    OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
-}")
+    OUTPUT_JUMP ("jeq %l0", "fjeq %l0", "jeq %l0");
+})
 
 (define_insn "bne"
   [(set (pc)
@@ -5849,13 +5704,12 @@
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "*
 {
   if (MOTOROLA)
-    OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
+    OUTPUT_JUMP ("jbne %l0", "fbne %l0", "jbne %l0");
   else
-    OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
-}")
+    OUTPUT_JUMP ("jne %l0", "fjne %l0", "jne %l0");
+})
 
 (define_insn "bgt"
   [(set (pc)
@@ -5864,12 +5718,12 @@
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "*
+{
   if (MOTOROLA)
-    OUTPUT_JUMP (\"jbgt %l0\", \"fbgt %l0\", 0);
+    OUTPUT_JUMP ("jbgt %l0", "fbgt %l0", 0);
   else
-    OUTPUT_JUMP (\"jgt %l0\", \"fjgt %l0\", 0);
-")
+    OUTPUT_JUMP ("jgt %l0", "fjgt %l0", 0);
+})
 
 (define_insn "bgtu"
   [(set (pc)
@@ -5878,9 +5732,9 @@
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "*
-  return MOTOROLA ? \"jbhi %l0\" : \"jhi %l0\";
-")
+{
+  return MOTOROLA ? "jbhi %l0" : "jhi %l0";
+})
 
 (define_insn "blt"
   [(set (pc)
@@ -5889,12 +5743,12 @@
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "*
+{
   if (MOTOROLA)
-    OUTPUT_JUMP (\"jblt %l0\", \"fblt %l0\", \"jbmi %l0\");
+    OUTPUT_JUMP ("jblt %l0", "fblt %l0", "jbmi %l0");
   else
-    OUTPUT_JUMP (\"jlt %l0\", \"fjlt %l0\", \"jmi %l0\");
-")
+    OUTPUT_JUMP ("jlt %l0", "fjlt %l0", "jmi %l0");
+})
 
 (define_insn "bltu"
   [(set (pc)
@@ -5903,9 +5757,9 @@
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "*
-  return MOTOROLA ? \"jbcs %l0\" : \"jcs %l0\";
-")
+{
+  return MOTOROLA ? "jbcs %l0" : "jcs %l0";
+})
 
 (define_insn "bge"
   [(set (pc)
@@ -5914,12 +5768,12 @@
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "*
+{
   if (MOTOROLA)
-    OUTPUT_JUMP (\"jbge %l0\", \"fbge %l0\", \"jbpl %l0\");
+    OUTPUT_JUMP ("jbge %l0", "fbge %l0", "jbpl %l0");
   else
-    OUTPUT_JUMP (\"jge %l0\", \"fjge %l0\", \"jpl %l0\");
-")
+    OUTPUT_JUMP ("jge %l0", "fjge %l0", "jpl %l0");
+})
 
 (define_insn "bgeu"
   [(set (pc)
@@ -5928,9 +5782,9 @@
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "*
-  return MOTOROLA ? \"jbcc %l0\" : \"jcc %l0\";
-")
+{
+  return MOTOROLA ? "jbcc %l0" : "jcc %l0";
+})
 
 (define_insn "ble"
   [(set (pc)
@@ -5939,12 +5793,12 @@
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "*
+{
   if (MOTOROLA)
-    OUTPUT_JUMP (\"jble %l0\", \"fble %l0\", 0);
+    OUTPUT_JUMP ("jble %l0", "fble %l0", 0);
   else
-    OUTPUT_JUMP (\"jle %l0\", \"fjle %l0\", 0);
-")
+    OUTPUT_JUMP ("jle %l0", "fjle %l0", 0);
+})
 
 (define_insn "bleu"
   [(set (pc)
@@ -5953,9 +5807,9 @@
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "*
-  return MOTOROLA ? \"jbls %l0\" : \"jls %l0\";
-")
+{
+  return MOTOROLA ? "jbls %l0" : "jls %l0";
+})
 
 (define_insn "bordered"
   [(set (pc)
@@ -6062,13 +5916,12 @@
 		      (pc)
 		      (label_ref (match_operand 0 "" ""))))]
   ""
-  "*
 {
   if (MOTOROLA)
-    OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
+    OUTPUT_JUMP ("jbne %l0", "fbne %l0", "jbne %l0");
   else
-    OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
-}")
+    OUTPUT_JUMP ("jne %l0", "fjne %l0", "jne %l0");
+})
 
 (define_insn ""
   [(set (pc)
@@ -6077,13 +5930,12 @@
 		      (pc)
 		      (label_ref (match_operand 0 "" ""))))]
   ""
-  "*
 {
   if (MOTOROLA)
-    OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
+    OUTPUT_JUMP ("jbeq %l0", "fbeq %l0", "jbeq %l0");
   else
-    OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
-}")
+    OUTPUT_JUMP ("jeq %l0", "fjeq %l0", "jeq %l0");
+})
 
 (define_insn ""
   [(set (pc)
@@ -6092,12 +5944,12 @@
 		      (pc)
 		      (label_ref (match_operand 0 "" ""))))]
   ""
-  "*
+{
   if (MOTOROLA)
-    OUTPUT_JUMP (\"jble %l0\", \"fbngt %l0\", 0);
+    OUTPUT_JUMP ("jble %l0", "fbngt %l0", 0);
   else
-    OUTPUT_JUMP (\"jle %l0\", \"fjngt %l0\", 0);
-")
+    OUTPUT_JUMP ("jle %l0", "fjngt %l0", 0);
+})
 
 (define_insn ""
   [(set (pc)
@@ -6106,9 +5958,9 @@
 		      (pc)
 		      (label_ref (match_operand 0 "" ""))))]
   ""
-  "*
-  return MOTOROLA ? \"jbls %l0\" : \"jls %l0\";
-")
+{
+  return MOTOROLA ? "jbls %l0" : "jls %l0";
+})
 
 (define_insn ""
   [(set (pc)
@@ -6117,12 +5969,12 @@
 		      (pc)
 		      (label_ref (match_operand 0 "" ""))))]
   ""
-  "*
+{
   if (MOTOROLA)
-    OUTPUT_JUMP (\"jbge %l0\", \"fbnlt %l0\", \"jbpl %l0\");
+    OUTPUT_JUMP ("jbge %l0", "fbnlt %l0", "jbpl %l0");
   else
-    OUTPUT_JUMP (\"jge %l0\", \"fjnlt %l0\", \"jpl %l0\");
-")
+    OUTPUT_JUMP ("jge %l0", "fjnlt %l0", "jpl %l0");
+})
 
 (define_insn ""
   [(set (pc)
@@ -6131,9 +5983,9 @@
 		      (pc)
 		      (label_ref (match_operand 0 "" ""))))]
   ""
-  "*
-  return MOTOROLA ? \"jbcc %l0\" : \"jcc %l0\";
-")
+{
+  return MOTOROLA ? "jbcc %l0" : "jcc %l0";
+})
 
 (define_insn ""
   [(set (pc)
@@ -6142,12 +5994,12 @@
 		      (pc)
 		      (label_ref (match_operand 0 "" ""))))]
   ""
-  "*
+{
   if (MOTOROLA)
-    OUTPUT_JUMP (\"jblt %l0\", \"fbnge %l0\", \"jbmi %l0\");
+    OUTPUT_JUMP ("jblt %l0", "fbnge %l0", "jbmi %l0");
   else
-    OUTPUT_JUMP (\"jlt %l0\", \"fjnge %l0\", \"jmi %l0\");
-")
+    OUTPUT_JUMP ("jlt %l0", "fjnge %l0", "jmi %l0");
+})
 
 (define_insn ""
   [(set (pc)
@@ -6156,9 +6008,9 @@
 		      (pc)
 		      (label_ref (match_operand 0 "" ""))))]
   ""
-  "*
-  return MOTOROLA ? \"jbcs %l0\" : \"jcs %l0\";
-")
+{
+  return MOTOROLA ? "jbcs %l0" : "jcs %l0";
+})
 
 (define_insn ""
   [(set (pc)
@@ -6167,12 +6019,12 @@
 		      (pc)
 		      (label_ref (match_operand 0 "" ""))))]
   ""
-  "*
+{
   if (MOTOROLA)
-    OUTPUT_JUMP (\"jbgt %l0\", \"fbnle %l0\", 0);
+    OUTPUT_JUMP ("jbgt %l0", "fbnle %l0", 0);
   else
-    OUTPUT_JUMP (\"jgt %l0\", \"fjnle %l0\", 0);
-")
+    OUTPUT_JUMP ("jgt %l0", "fjnle %l0", 0);
+})
 
 (define_insn ""
   [(set (pc)
@@ -6181,9 +6033,9 @@
 		      (pc)
 		      (label_ref (match_operand 0 "" ""))))]
   ""
-  "*
-  return MOTOROLA ? \"jbhi %l0\" : \"jhi %l0\";
-")
+{
+  return MOTOROLA ? "jbhi %l0" : "jhi %l0";
+})
 
 (define_insn "*bordered_rev"
   [(set (pc)
@@ -6274,13 +6126,10 @@
   [(set (pc)
 	(label_ref (match_operand 0 "" "")))]
   ""
-  "*
-  return MOTOROLA ? \"jbra %l0\" : \"jra %l0\";
-")
+{
+  return MOTOROLA ? "jbra %l0" : "jra %l0";
+})
 
-;; We support two different ways of handling dispatch tables.
-;; The NeXT uses absolute tables, and other machines use relative.
-;; This define_expand can generate either kind.
 (define_expand "tablejump"
   [(parallel [(set (pc) (match_operand 0 "" ""))
 	      (use (label_ref (match_operand 1 "" "")))])]
@@ -6298,9 +6147,9 @@
   [(set (pc) (match_operand:SI 0 "register_operand" "a"))
    (use (label_ref (match_operand 1 "" "")))]
   ""
-  "*
-  return MOTOROLA ? \"jmp (%0)\" : \"jmp %0@\";
-")
+{
+  return MOTOROLA ? "jmp (%0)" : "jmp %0@";
+})
 
 ;; Jump to variable address from dispatch table of relative addresses.
 (define_insn ""
@@ -6309,51 +6158,51 @@
 		 (sign_extend:SI (match_operand:HI 0 "register_operand" "r"))))
    (use (label_ref (match_operand 1 "" "")))]
   ""
-  "*
+{
 #ifdef ASM_RETURN_CASE_JUMP
- ASM_RETURN_CASE_JUMP;
+  ASM_RETURN_CASE_JUMP;
 #else
 #ifdef SGS
 #ifdef ASM_OUTPUT_CASE_LABEL
   if (TARGET_COLDFIRE) 
     {
       if (ADDRESS_REG_P (operands[0]))
-	return \"jmp 6(%%pc,%0.l)\";
+	return "jmp 6(%%pc,%0.l)";
       else
-	return \"ext%.l %0\;jmp 6(%%pc,%0.l)\";
+	return "ext%.l %0\;jmp 6(%%pc,%0.l)";
     }
   else
-    return \"jmp 6(%%pc,%0.w)\";
+    return "jmp 6(%%pc,%0.w)";
 #else
   if (TARGET_COLDFIRE)
     {
       if (ADDRESS_REG_P (operands[0]))
-	return \"jmp 2(%%pc,%0.l)\";
+	return "jmp 2(%%pc,%0.l)";
       else
-	return \"extl %0\;jmp 2(%%pc,%0.l)\";
+	return "extl %0\;jmp 2(%%pc,%0.l)";
     }
   else
-    return \"jmp 2(%%pc,%0.w)\";
+    return "jmp 2(%%pc,%0.w)";
 #endif
 #else /* not SGS */
   if (TARGET_COLDFIRE)
     {
       if (ADDRESS_REG_P (operands[0]))
 	{
-	  return MOTOROLA ? \"jmp (2,pc,%0.l)\" : \"jmp pc@(2,%0:l)\";
+	  return MOTOROLA ? "jmp (2,pc,%0.l)" : "jmp pc@(2,%0:l)";
 	}
       else if (MOTOROLA)
-	return \"ext%.l %0\;jmp (2,pc,%0.l)\";
+	return "ext%.l %0\;jmp (2,pc,%0.l)";
       else
-	return \"extl %0\;jmp pc@(2,%0:l)\";
+	return "extl %0\;jmp pc@(2,%0:l)";
     }
   else
     {
-      return MOTOROLA ? \"jmp (2,pc,%0.w)\" : \"jmp pc@(2,%0:w)\";
+      return MOTOROLA ? "jmp (2,pc,%0.w)" : "jmp pc@(2,%0:w)";
     }
 #endif
 #endif
-")
+})
 
 ;; Decrement-and-branch insns.
 (define_insn ""
@@ -6367,27 +6216,26 @@
 	(plus:HI (match_dup 0)
 		 (const_int -1)))]
   "!TARGET_COLDFIRE"
-  "*
 {
   CC_STATUS_INIT;
   if (DATA_REG_P (operands[0]))
-    return \"dbra %0,%l1\";
+    return "dbra %0,%l1";
   if (GET_CODE (operands[0]) == MEM)
     {
       if (MOTOROLA)
-	return \"subq%.w %#1,%0\;jbcc %l1\";
+	return "subq%.w %#1,%0\;jbcc %l1";
       else
-	return \"subqw %#1,%0\;jcc %l1\";
+	return "subqw %#1,%0\;jcc %l1";
     }
   if (MOTOROLA)
 #ifdef SGS_CMP_ORDER
-    return \"subq%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
+    return "subq%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1";
 #else /* not SGS_CMP_ORDER */
-    return \"subq%.w %#1,%0\;cmp%.w %#-1,%0\;jbne %l1\";
+    return "subq%.w %#1,%0\;cmp%.w %#-1,%0\;jbne %l1";
 #endif
   else
-    return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
-}")
+    return "subqw %#1,%0\;cmpw %#-1,%0\;jne %l1";
+})
 
 (define_insn ""
   [(set (pc)
@@ -6400,30 +6248,29 @@
 	(plus:SI (match_dup 0)
 		 (const_int -1)))]
   "!TARGET_COLDFIRE"
-  "*
 {
   CC_STATUS_INIT;
   if (MOTOROLA)
     {
       if (DATA_REG_P (operands[0]))
-        return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
+        return "dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1";
       if (GET_CODE (operands[0]) == MEM)
-        return \"subq%.l %#1,%0\;jbcc %l1\";
+        return "subq%.l %#1,%0\;jbcc %l1";
 #ifdef SGS_CMP_ORDER
-      return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
+      return "subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1";
 #else /* not SGS_CMP_ORDER */
-      return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
+      return "subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1";
 #endif /* not SGS_CMP_ORDER */
     }
   else
     {
       if (DATA_REG_P (operands[0]))
-        return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
+        return "dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1";
       if (GET_CODE (operands[0]) == MEM)
-        return \"subql %#1,%0\;jcc %l1\";
-      return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
+        return "subql %#1,%0\;jcc %l1";
+      return "subql %#1,%0\;cmpl %#-1,%0\;jne %l1";
     }
-}")
+})
 
 ;; Two dbra patterns that use REG_NOTES info generated by strength_reduce.
 
@@ -6439,30 +6286,29 @@
 	(plus:HI (match_dup 0)
 		 (const_int -1)))]
   "!TARGET_COLDFIRE && find_reg_note (insn, REG_NONNEG, 0)"
-  "*
 {
   CC_STATUS_INIT;
   if (MOTOROLA)
     {
       if (DATA_REG_P (operands[0]))
-        return \"dbra %0,%l1\";
+        return "dbra %0,%l1";
       if (GET_CODE (operands[0]) == MEM)
-        return \"subq%.w %#1,%0\;jbcc %l1\";
+        return "subq%.w %#1,%0\;jbcc %l1";
 #ifdef SGS_CMP_ORDER
-      return \"subq.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
+      return "subq.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1";
 #else /* not SGS_CMP_ORDER */
-      return \"subq.w %#1,%0\;cmp.w %#-1,%0\;jbne %l1\";
+      return "subq.w %#1,%0\;cmp.w %#-1,%0\;jbne %l1";
 #endif /* not SGS_CMP_ORDER */
     }
   else
     {
       if (DATA_REG_P (operands[0]))
-        return \"dbra %0,%l1\";
+        return "dbra %0,%l1";
       if (GET_CODE (operands[0]) == MEM)
-        return \"subqw %#1,%0\;jcc %l1\";
-      return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
+        return "subqw %#1,%0\;jcc %l1";
+      return "subqw %#1,%0\;cmpw %#-1,%0\;jne %l1";
     }
-}")
+})
 
 (define_expand "decrement_and_branch_until_zero"
   [(parallel [(set (pc)
@@ -6490,30 +6336,29 @@
 	(plus:SI (match_dup 0)
 		 (const_int -1)))]
   "!TARGET_COLDFIRE && find_reg_note (insn, REG_NONNEG, 0)"
-  "*
 {
   CC_STATUS_INIT;
   if (MOTOROLA)
     {
       if (DATA_REG_P (operands[0]))
-        return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
+        return "dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1";
       if (GET_CODE (operands[0]) == MEM)
-        return \"subq%.l %#1,%0\;jbcc %l1\";
+        return "subq%.l %#1,%0\;jbcc %l1";
 #ifdef SGS_CMP_ORDER
-      return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
+      return "subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1";
 #else /* not SGS_CMP_ORDER */
-      return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
+      return "subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1";
 #endif /* not SGS_CMP_ORDER */
     }
   else
     {
       if (DATA_REG_P (operands[0]))
-        return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
+        return "dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1";
       if (GET_CODE (operands[0]) == MEM)
-        return \"subql %#1,%0\;jcc %l1\";
-      return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
+        return "subql %#1,%0\;jcc %l1";
+      return "subql %#1,%0\;cmpl %#-1,%0\;jne %l1";
     }
-}")
+})
 
 
 ;; For PIC calls, in order to be able to support
@@ -6573,13 +6418,13 @@
   ;; Operand 1 not really used on the m68000.
 
   "! flag_pic"
-  "*
+{
 #if MOTOROLA && !defined (USE_GAS)
-  return \"jsr %0\";
+  return "jsr %0";
 #else
-  return \"jbsr %0\";
+  return "jbsr %0";
 #endif
-")
+})
 
 ;; This is a PIC call sequence.
 (define_insn ""
@@ -6588,10 +6433,10 @@
   ;; Operand 1 not really used on the m68000.
 
   "flag_pic"
-  "*
+{
   m68k_output_pic_call(operands[0]);
-  return \"\";
-")
+  return "";
+})
 
 ;; Call subroutine, returning value in operand 0
 ;; (which must be a hard register).
@@ -6615,13 +6460,13 @@
 	      (match_operand:SI 2 "general_operand" "g")))]
   ;; Operand 2 not really used on the m68000.
   "! flag_pic"
-  "*
+{
 #if MOTOROLA && !defined (USE_GAS)
-  return \"jsr %1\";
+  return "jsr %1";
 #else
-  return \"jbsr %1\";
+  return "jbsr %1";
 #endif
-")
+})
 
 ;; This is a PIC call_value
 (define_insn ""
@@ -6630,10 +6475,10 @@
 	      (match_operand:SI 2 "general_operand" "g")))]
   ;; Operand 2 not really used on the m68000.
   "flag_pic"
-  "*
+{
   m68k_output_pic_call(operands[1]);
-  return \"\";
-")
+  return "";
+})
 
 ;; Call subroutine returning any type.
 
@@ -6681,13 +6526,12 @@
 (define_insn "return"
   [(return)]
   "USE_RETURN_INSN"
-  "*
 {
   if (current_function_pops_args == 0)
-    return \"rts\";
+    return "rts";
   operands[0] = GEN_INT (current_function_pops_args);
-  return \"rtd %0\";
-}")
+  return "rtd %0";
+})
 
 (define_insn "indirect_jump"
   [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
@@ -6700,7 +6544,6 @@
   [(set (match_operand:SI 0 "nonimmediate_operand" "=a")
 	(match_operand:QI 1 "address_operand" "p"))]
   ""
-  "*
 {
   /* Recognize an insn that refers to a table of offsets.  Such an insn will
      need to refer to a label on the insn.  So output one.  Use the
@@ -6714,14 +6557,14 @@
       rtx labelref = XEXP (operands[1], 1);
 #if MOTOROLA && !defined (SGS_SWITCH_TABLES)
 #ifdef SGS
-      asm_fprintf (asm_out_file, \"\\tset %LLI%d,.+2\\n\",
+      asm_fprintf (asm_out_file, "\\tset %LLI%d,.+2\\n",
 		   CODE_LABEL_NUMBER (XEXP (labelref, 0)));
 #else /* not SGS */
-      asm_fprintf (asm_out_file, \"\\t.set %LLI%d,.+2\\n\",
+      asm_fprintf (asm_out_file, "\\t.set %LLI%d,.+2\\n",
 	           CODE_LABEL_NUMBER (XEXP (labelref, 0)));
 #endif /* not SGS */
 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
-      (*targetm.asm_out.internal_label) (asm_out_file, \"LI\",
+      (*targetm.asm_out.internal_label) (asm_out_file, "LI",
 				 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
 #ifdef SGS_SWITCH_TABLES
       /* Set flag saying we need to define the symbol
@@ -6731,8 +6574,8 @@
 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
     }
 
-  return \"lea %a1,%0\";
-}")
+  return "lea %a1,%0";
+})
 
 ;; This is the first machine-dependent peephole optimization.
 ;; It is useful when a floating value is returned from a function call
@@ -6744,15 +6587,13 @@
    (set (match_operand:DF 0 "register_operand" "=f")
 	(match_operand:DF 1 "register_operand" "ad"))]
   "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
-  "*
 {
   rtx xoperands[2];
   xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
-  output_asm_insn (\"move%.l %1,%@\", xoperands);
-  output_asm_insn (\"move%.l %1,%-\", operands);
-  return \"fmove%.d %+,%0\";
-}
-")
+  output_asm_insn ("move%.l %1,%@", xoperands);
+  output_asm_insn ("move%.l %1,%-", operands);
+  return "fmove%.d %+,%0";
+})
 
 ;; Optimize a stack-adjust followed by a push of an argument.
 ;; This is said to happen frequently with -msoft-float
@@ -6765,7 +6606,6 @@
 	(match_operand:SF 2 "general_operand" "rmfF"))]
   "INTVAL (operands[0]) >= 4
    && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
-  "*
 {
   if (INTVAL (operands[0]) > 4)
     {
@@ -6775,31 +6615,31 @@
       if (INTVAL (xoperands[1]) <= 8)
 	{
 	  if (!TARGET_COLDFIRE)
-	    output_asm_insn (\"addq%.w %1,%0\", xoperands);
+	    output_asm_insn ("addq%.w %1,%0", xoperands);
 	  else
-	    output_asm_insn (\"addq%.l %1,%0\", xoperands);
+	    output_asm_insn ("addq%.l %1,%0", xoperands);
 	}
       else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16) 
 	{
 	  xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 8);
-	  output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
+	  output_asm_insn ("addq%.w %#8,%0\;addq%.w %1,%0", xoperands);
 	}
       else if (INTVAL (xoperands[1]) <= 0x7FFF)
         {
 	  if (TARGET_68040)
-	    output_asm_insn (\"add%.w %1,%0\", xoperands);
+	    output_asm_insn ("add%.w %1,%0", xoperands);
 	  else if (MOTOROLA)
-	    output_asm_insn (\"lea (%c1,%0),%0\", xoperands);
+	    output_asm_insn ("lea (%c1,%0),%0", xoperands);
 	  else
-	    output_asm_insn (\"lea %0@(%c1),%0\", xoperands);
+	    output_asm_insn ("lea %0@(%c1),%0", xoperands);
         }
       else
-        output_asm_insn (\"add%.l %1,%0\", xoperands);
+        output_asm_insn ("add%.l %1,%0", xoperands);
     }
   if (FP_REG_P (operands[2]))
-    return \"fmove%.s %2,%@\";
-  return \"move%.l %2,%@\";
-}")
+    return "fmove%.s %2,%@";
+  return "move%.l %2,%@";
+})
 
 ;; Speed up stack adjust followed by a fullword fixedpoint push.
 
@@ -6810,7 +6650,6 @@
 	(match_operand:SI 2 "general_operand" "g"))]
   "INTVAL (operands[0]) >= 4
    && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
-  "*
 {
   if (INTVAL (operands[0]) > 4)
     {
@@ -6820,31 +6659,31 @@
       if (INTVAL (xoperands[1]) <= 8)
 	{
 	  if (!TARGET_COLDFIRE)
-	    output_asm_insn (\"addq%.w %1,%0\", xoperands);
+	    output_asm_insn ("addq%.w %1,%0", xoperands);
 	  else
-	    output_asm_insn (\"addq%.l %1,%0\", xoperands);
+	    output_asm_insn ("addq%.l %1,%0", xoperands);
 	}
       else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16)
 	{
 	  xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 8);
-	  output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
+	  output_asm_insn ("addq%.w %#8,%0\;addq%.w %1,%0", xoperands);
 	}
       else if (INTVAL (xoperands[1]) <= 0x7FFF)
         {
 	  if (TARGET_68040)
-	    output_asm_insn (\"add%.w %1,%0\", xoperands);
+	    output_asm_insn ("add%.w %1,%0", xoperands);
 	  else if (MOTOROLA)
-	    output_asm_insn (\"lea (%c1,%0),%0\", xoperands);
+	    output_asm_insn ("lea (%c1,%0),%0", xoperands);
 	  else
-	    output_asm_insn (\"lea %0@(%c1),%0\", xoperands);
+	    output_asm_insn ("lea %0@(%c1),%0", xoperands);
         }
       else
-        output_asm_insn (\"add%.l %1,%0\", xoperands);
+        output_asm_insn ("add%.l %1,%0", xoperands);
     }
   if (operands[2] == const0_rtx)
-    return \"clr%.l %@\";
-  return \"move%.l %2,%@\";
-}")
+    return "clr%.l %@";
+  return "move%.l %2,%@";
+})
 
 ;; Speed up pushing a single byte but leaving four bytes of space.
 
@@ -6853,23 +6692,22 @@
 	(match_operand:QI 1 "general_operand" "dami"))
    (set (reg:SI 15) (minus:SI (reg:SI 15) (const_int 2)))]
   "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
-  "*
 {
   rtx xoperands[4];
 
   if (GET_CODE (operands[1]) == REG)
-    return \"move%.l %1,%-\";
+    return "move%.l %1,%-";
 
   xoperands[1] = operands[1];
   xoperands[2]
     = gen_rtx_MEM (QImode, plus_constant (stack_pointer_rtx, 3));
   xoperands[3] = stack_pointer_rtx;
   if (!TARGET_COLDFIRE)
-    output_asm_insn (\"subq%.w %#4,%3\;move%.b %1,%2\", xoperands);
+    output_asm_insn ("subq%.w %#4,%3\;move%.b %1,%2", xoperands);
   else
-    output_asm_insn (\"subq%.l %#4,%3\;move%.b %1,%2\", xoperands);
-  return \"\";
-}")
+    output_asm_insn ("subq%.l %#4,%3\;move%.b %1,%2", xoperands);
+  return "";
+})
 
 (define_peephole
   [(set (match_operand:SI 0 "register_operand" "=d")
@@ -6877,7 +6715,6 @@
    (set (strict_low_part (subreg:HI (match_dup 0) 2))
 	(match_operand:HI 1 "general_operand" "rmn"))]
   "strict_low_part_peephole_ok (HImode, prev_nonnote_insn (insn), operands[0])"
-  "*
 {
   if (GET_CODE (operands[1]) == CONST_INT)
     {
@@ -6889,10 +6726,10 @@
 	  && ((TARGET_68020 || TARGET_COLDFIRE)
 	      || !(GET_CODE (operands[0]) == MEM
 		   && MEM_VOLATILE_P (operands[0]))))
-	return \"clr%.w %0\";
+	return "clr%.w %0";
     }
-  return \"move%.w %1,%0\";
-}")
+  return "move%.w %1,%0";
+})
 
 ;; dbCC peepholes
 ;;
@@ -6927,12 +6764,11 @@
 	  (plus:HI (match_dup 0)
 		   (const_int -1)))])]
   "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
-  "*
 {
   CC_STATUS_INIT;
   output_dbcc_and_branch (operands);
-  return \"\";
-}")
+  return "";
+})
 
 (define_peephole
   [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
@@ -6950,12 +6786,11 @@
 	  (plus:SI (match_dup 0)
 		   (const_int -1)))])]
   "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
-  "*
 {
   CC_STATUS_INIT;
   output_dbcc_and_branch (operands);
-  return \"\";
-}")
+  return "";
+})
 
 (define_peephole
   [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
@@ -6974,12 +6809,11 @@
 	  (plus:HI (match_dup 0)
 		   (const_int -1)))])]
   "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
-  "*
 {
   CC_STATUS_INIT;
   output_dbcc_and_branch (operands);
-  return \"\";
-}")
+  return "";
+})
 
 (define_peephole
   [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
@@ -6998,12 +6832,11 @@
 	  (plus:SI (match_dup 0)
 		   (const_int -1)))])]
   "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
-  "*
 {
   CC_STATUS_INIT;
   output_dbcc_and_branch (operands);
-  return \"\";
-}")
+  return "";
+})
 
 
 (define_expand "tstxf"
@@ -7016,11 +6849,10 @@
   [(set (cc0)
 	(match_operand:XF 0 "nonimmediate_operand" "fm"))]
   "TARGET_68881"
-  "*
 {
   cc_status.flags = CC_IN_68881;
-  return \"ftst%.x %0\";
-}")
+  return "ftst%.x %0";
+})
 
 (define_expand "cmpxf"
   [(set (cc0)
@@ -7034,37 +6866,35 @@
 	(compare (match_operand:XF 0 "nonimmediate_operand" "f,m")
 		 (match_operand:XF 1 "nonimmediate_operand" "fm,f")))]
   "TARGET_68881"
-  "*
 {
   cc_status.flags = CC_IN_68881;
 #ifdef SGS_CMP_ORDER
   if (REG_P (operands[0]))
     {
       if (REG_P (operands[1]))
-	return \"fcmp%.x %0,%1\";
+	return "fcmp%.x %0,%1";
       else
-        return \"fcmp%.x %0,%f1\";
+        return "fcmp%.x %0,%f1";
     }
   cc_status.flags |= CC_REVERSED;
-  return \"fcmp%.x %1,%f0\";
+  return "fcmp%.x %1,%f0";
 #else
   if (REG_P (operands[0]))
     {
       if (REG_P (operands[1]))
-	return \"fcmp%.x %1,%0\";
+	return "fcmp%.x %1,%0";
       else
-        return \"fcmp%.x %f1,%0\";
+        return "fcmp%.x %f1,%0";
     }
   cc_status.flags |= CC_REVERSED;
-  return \"fcmp%.x %f0,%1\";
+  return "fcmp%.x %f0,%1";
 #endif
-}")
+})
 
 (define_insn "extendsfxf2"
   [(set (match_operand:XF 0 "nonimmediate_operand" "=fm,f")
 	(float_extend:XF (match_operand:SF 1 "general_operand" "f,rmF")))]
   "TARGET_68881"
-  "*
 {
   if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
     {
@@ -7074,22 +6904,22 @@
 	     NOTICE_UPDATE_CC has already assumed that the
 	     cc will be set.  So cancel what it did.  */
 	  cc_status = cc_prev_status;
-	  return \"\";
+	  return "";
 	}
-      return \"f%$move%.x %1,%0\";
+      return "f%$move%.x %1,%0";
     }
   if (FP_REG_P (operands[0]))
     {
       if (FP_REG_P (operands[1]))
-	return \"f%$move%.x %1,%0\";
+	return "f%$move%.x %1,%0";
       else if (ADDRESS_REG_P (operands[1]))
-	return \"move%.l %1,%-\;f%$move%.s %+,%0\";
+	return "move%.l %1,%-\;f%$move%.s %+,%0";
       else if (GET_CODE (operands[1]) == CONST_DOUBLE)
 	return output_move_const_single (operands);
-      return \"f%$move%.s %f1,%0\";
+      return "f%$move%.s %f1,%0";
     }
-  return \"fmove%.x %f1,%0\";
-}")
+  return "fmove%.x %f1,%0";
+})
 
 
 (define_insn "extenddfxf2"
@@ -7097,7 +6927,6 @@
 	(float_extend:XF
           (match_operand:DF 1 "general_operand" "f,rmE")))]
   "TARGET_68881"
-  "*
 {
   if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
     {
@@ -7107,9 +6936,9 @@
 	     NOTICE_UPDATE_CC has already assumed that the
 	     cc will be set.  So cancel what it did.  */
 	  cc_status = cc_prev_status;
-	  return \"\";
+	  return "";
 	}
-      return \"fmove%.x %1,%0\";
+      return "fmove%.x %1,%0";
     }
   if (FP_REG_P (operands[0]))
     {
@@ -7117,32 +6946,31 @@
 	{
 	  rtx xoperands[2];
 	  xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
-	  output_asm_insn (\"move%.l %1,%-\", xoperands);
-	  output_asm_insn (\"move%.l %1,%-\", operands);
-	  return \"f%&move%.d %+,%0\";
+	  output_asm_insn ("move%.l %1,%-", xoperands);
+	  output_asm_insn ("move%.l %1,%-", operands);
+	  return "f%&move%.d %+,%0";
 	}
       if (GET_CODE (operands[1]) == CONST_DOUBLE)
 	return output_move_const_double (operands);
-      return \"f%&move%.d %f1,%0\";
+      return "f%&move%.d %f1,%0";
     }
-  return \"fmove%.x %f1,%0\";
-}")
+  return "fmove%.x %f1,%0";
+})
 
 (define_insn "truncxfdf2"
   [(set (match_operand:DF 0 "nonimmediate_operand" "=m,!r")
 	(float_truncate:DF
           (match_operand:XF 1 "general_operand" "f,f")))]
   "TARGET_68881"
-  "*
 {
   if (REG_P (operands[0]))
     {
-      output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
+      output_asm_insn ("fmove%.d %f1,%-\;move%.l %+,%0", operands);
       operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-      return \"move%.l %+,%0\";
+      return "move%.l %+,%0";
     }
-  return \"fmove%.d %f1,%0\";
-}")
+  return "fmove%.d %f1,%0";
+})
 
 (define_insn "truncxfsf2"
   [(set (match_operand:SF 0 "nonimmediate_operand" "=dm")
@@ -7173,12 +7001,11 @@
   [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
 	(fix:XF (match_operand:XF 1 "general_operand" "fFm")))]
   "TARGET_68881"
-  "*
 {
   if (FP_REG_P (operands[1]))
-    return \"fintrz%.x %f1,%0\";
-  return \"fintrz%.x %f1,%0\";
-}")
+    return "fintrz%.x %f1,%0";
+  return "fintrz%.x %f1,%0";
+})
 
 (define_insn "fixxfqi2"
   [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
@@ -7224,12 +7051,11 @@
 	(plus:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
 		 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
   "TARGET_68881"
-  "*
 {
   if (REG_P (operands[2]))
-    return \"fadd%.x %2,%0\";
-  return \"fadd%.x %f2,%0\";
-}")
+    return "fadd%.x %2,%0";
+  return "fadd%.x %f2,%0";
+})
 
 (define_insn ""
   [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
@@ -7257,12 +7083,11 @@
 	(minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
 		  (match_operand:XF 2 "nonimmediate_operand" "fm")))]
   "TARGET_68881"
-  "*
 {
   if (REG_P (operands[2]))
-    return \"fsub%.x %2,%0\";
-  return \"fsub%.x %f2,%0\";
-}")
+    return "fsub%.x %2,%0";
+  return "fsub%.x %f2,%0";
+})
 
 (define_insn ""
   [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
@@ -7290,12 +7115,11 @@
 	(mult:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
 		 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
   "TARGET_68881"
-  "*
 {
   if (REG_P (operands[2]))
-    return \"fmul%.x %2,%0\";
-  return \"fmul%.x %f2,%0\";
-}")
+    return "fmul%.x %2,%0";
+  return "fmul%.x %f2,%0";
+})
 
 (define_insn ""
   [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
@@ -7323,12 +7147,11 @@
 	(div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
 		(match_operand:XF 2 "nonimmediate_operand" "fm")))]
   "TARGET_68881"
-  "*
 {
   if (REG_P (operands[2]))
-    return \"fdiv%.x %2,%0\";
-  return \"fdiv%.x %f2,%0\";
-}")
+    return "fdiv%.x %2,%0";
+  return "fdiv%.x %f2,%0";
+})
 
 (define_expand "negxf2"
   [(set (match_operand:XF 0 "nonimmediate_operand" "")
@@ -7370,12 +7193,11 @@
   [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
 	(neg:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
   "TARGET_68881"
-  "*
 {
   if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
-    return \"fneg%.x %1,%0\";
-  return \"fneg%.x %f1,%0\";
-}")
+    return "fneg%.x %1,%0";
+  return "fneg%.x %f1,%0";
+})
 
 (define_expand "absxf2"
   [(set (match_operand:XF 0 "nonimmediate_operand" "")
@@ -7417,12 +7239,11 @@
   [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
 	(abs:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
   "TARGET_68881"
-  "*
 {
   if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
-    return \"fabs%.x %1,%0\";
-  return \"fabs%.x %f1,%0\";
-}")
+    return "fabs%.x %1,%0";
+  return "fabs%.x %f1,%0";
+})
 
 (define_insn "sqrtxf2"
   [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
@@ -7434,25 +7255,23 @@
   [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
 	(unspec:SF [(match_operand:SF 1 "general_operand" "fm")] UNSPEC_SIN))]
   "TARGET_68881 && flag_unsafe_math_optimizations"
-  "*
 {
   if (FP_REG_P (operands[1]))
-    return \"fsin%.x %1,%0\";
+    return "fsin%.x %1,%0";
   else
-    return \"fsin%.s %1,%0\";
-}")
+    return "fsin%.s %1,%0";
+})
 
 (define_insn "sindf2"
   [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
 	(unspec:DF [(match_operand:DF 1 "general_operand" "fm")] UNSPEC_SIN))]
   "TARGET_68881 && flag_unsafe_math_optimizations"
-  "*
 {
   if (FP_REG_P (operands[1]))
-    return \"fsin%.x %1,%0\";
+    return "fsin%.x %1,%0";
   else
-    return \"fsin%.d %1,%0\";
-}")
+    return "fsin%.d %1,%0";
+})
 
 (define_insn "sinxf2"
   [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
@@ -7464,25 +7283,23 @@
   [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
 	(unspec:SF [(match_operand:SF 1 "general_operand" "fm")] UNSPEC_COS))]
   "TARGET_68881 && flag_unsafe_math_optimizations"
-  "*
 {
   if (FP_REG_P (operands[1]))
-    return \"fcos%.x %1,%0\";
+    return "fcos%.x %1,%0";
   else
-    return \"fcos%.s %1,%0\";
-}")
+    return "fcos%.s %1,%0";
+})
 
 (define_insn "cosdf2"
   [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
 	(unspec:DF [(match_operand:DF 1 "general_operand" "fm")] UNSPEC_COS))]
   "TARGET_68881 && flag_unsafe_math_optimizations"
-  "*
 {
   if (FP_REG_P (operands[1]))
-    return \"fcos%.x %1,%0\";
+    return "fcos%.x %1,%0";
   else
-    return \"fcos%.d %1,%0\";
-}")
+    return "fcos%.d %1,%0";
+})
 
 (define_insn "cosxf2"
   [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
@@ -7500,20 +7317,19 @@
 			    [(cc0) (const_int 0)])
 	    (match_operand:SI 1 "const_int_operand" "I"))]
   "TARGET_68020 && ! flags_in_68881 ()"
-  "*
 {
   switch (GET_CODE (operands[0]))
   {
-  case EQ:  return \"trapeq\";
-  case NE:  return \"trapne\";
-  case GT:  return \"trapgt\";
-  case GTU: return \"traphi\";
-  case LT:  return \"traplt\";
-  case LTU: return \"trapcs\";
-  case GE:  return \"trapge\";
-  case GEU: return \"trapcc\";
-  case LE:  return \"traple\";
-  case LEU: return \"trapls\";
+  case EQ:  return "trapeq";
+  case NE:  return "trapne";
+  case GT:  return "trapgt";
+  case GTU: return "traphi";
+  case LT:  return "traplt";
+  case LTU: return "trapcs";
+  case GE:  return "trapge";
+  case GEU: return "trapcc";
+  case LE:  return "traple";
+  case LEU: return "trapls";
   default: abort();
   }
-}")
+})