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| author | Vineet Gupta <vineetg@rivosinc.com> | 2023-10-06 11:21:51 -0700 |
|---|---|---|
| committer | Vineet Gupta <vineetg@rivosinc.com> | 2023-10-06 11:21:51 -0700 |
| commit | c1bc7513b1d76812752f70cc2ef7e0173dfb0014 (patch) | |
| tree | 381a0cba702d144581442db06b00b284a386bd9e /gcc | |
| parent | 837a12a2276938caa8e37434c0d896f14584a4f7 (diff) | |
| download | gcc-c1bc7513b1d76812752f70cc2ef7e0173dfb0014.zip gcc-c1bc7513b1d76812752f70cc2ef7e0173dfb0014.tar.gz gcc-c1bc7513b1d76812752f70cc2ef7e0173dfb0014.tar.bz2 | |
RISC-V: const: hide mvconst splitter from IRA
Vlad recently introduced a new gate @ira_in_progress, similar to
counterparts @{reload,lra}_in_progress.
Use this to hide the constant synthesis splitter from being recog* ()
by IRA register equivalence logic which is eager to undo the splits,
generating worse code for constants (and sometimes no code at all).
See PR/109279 (large constant), PR/110748 (const -0.0) ...
Granted the IRA logic is subsided with -fsched-pressure which is now
enabled for RISC-V backend, the gate makes this future-proof in
addition to helping with -O1 etc.
This fixes 1 addition test
========= Summary of gcc testsuite =========
| # of unexpected case / # of unique unexpected case
| gcc | g++ | gfortran |
rv32imac/ ilp32/ medlow | 416 / 103 | 13 / 6 | 67 / 12 |
rv32imafdc/ ilp32d/ medlow | 416 / 103 | 13 / 6 | 24 / 4 |
rv64imac/ lp64/ medlow | 417 / 104 | 9 / 3 | 67 / 12 |
rv64imafdc/ lp64d/ medlow | 416 / 103 | 5 / 2 | 6 / 1 |
Also similar to v1, this doesn't move RISC-V SPEC scores at all.
gcc/ChangeLog:
* config/riscv/riscv.md (mvconst_internal): Add !ira_in_progress.
Suggested-by: Jeff Law <jeffreyalaw@gmail.com>
Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/riscv/riscv.md | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 1ebe8f9..da84b93 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -1997,13 +1997,16 @@ ;; Pretend to have the ability to load complex const_int in order to get ;; better code generation around them. -;; ;; But avoid constants that are special cased elsewhere. +;; +;; Hide it from IRA register equiv recog* () to elide potential undoing of split +;; (define_insn_and_split "*mvconst_internal" [(set (match_operand:GPR 0 "register_operand" "=r") (match_operand:GPR 1 "splittable_const_int_operand" "i"))] - "!(p2m1_shift_operand (operands[1], <MODE>mode) - || high_mask_shift_operand (operands[1], <MODE>mode))" + "!ira_in_progress + && !(p2m1_shift_operand (operands[1], <MODE>mode) + || high_mask_shift_operand (operands[1], <MODE>mode))" "#" "&& 1" [(const_int 0)] |