rs6000.h (MAX_FIXED_MODE_SIZE): Define.

        * config/rs6000/rs6000.h (MAX_FIXED_MODE_SIZE): Define.

        * config/rs6000/rs6000.md (mfcr rlwinm patterns): Set length to 8.
        (mfcr rlwinm rlwinm patterns): Set length to 12.

From-SVN: r85808

3 files changed, 22 insertions, 9 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index a67eae27..3509bba 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2004-08-11 David Edelsohn  <edelsohn@gnu.org>
+
+	* config/rs6000/rs6000.h (MAX_FIXED_MODE_SIZE): Define.
+
+	* config/rs6000/rs6000.md (mfcr rlwinm patterns): Set length to 8.
+	(mfcr rlwinm rlwinm patterns): Set length to 12.
+
 2004-08-11  Andrew MacLeod  <amacleod@redhat.com>
 
 	* tree-flow-inline.h (get_def_ops, get_use_ops, get_v_may_def_ops,
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index f69b10c..4b7db3a 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -2103,6 +2103,12 @@ do {								\
 
 /* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */
 
+/* An integer expression for the size in bits of the largest integer machine
+   mode that should actually be used.  */
+
+/* Allow pairs of registers to be used, which is the intent of the default.  */
+#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode)
+
 /* Max number of bytes we can move from memory to memory
    in one reasonably fast instruction.  */
 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index aef44d5..8cd7063 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -11390,7 +11390,7 @@
 		(const_string "mfcrf")
 	   ]
 	(const_string "mfcr")))
-   (set_attr "length" "12")])
+   (set_attr "length" "8")])
 
 ;; Same as above, but get the GT bit.
 (define_insn "move_from_CR_eq_bit"
@@ -11399,7 +11399,7 @@
   "TARGET_E500"
   "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,1"
   [(set_attr "type" "mfcr")
-   (set_attr "length" "12")])
+   (set_attr "length" "8")])
 
 ;; Same as above, but get the OV/ORDERED bit.
 (define_insn "move_from_CR_ov_bit"
@@ -11408,7 +11408,7 @@
   "TARGET_ISEL"
   "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
   [(set_attr "type" "mfcr")
-   (set_attr "length" "12")])
+   (set_attr "length" "8")])
 
 (define_insn ""
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
@@ -11422,7 +11422,7 @@
 		(const_string "mfcrf")
 	   ]
 	(const_string "mfcr")))
-   (set_attr "length" "12")])
+   (set_attr "length" "8")])
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
@@ -11437,7 +11437,7 @@
    mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
    #"
   [(set_attr "type" "delayed_compare")
-   (set_attr "length" "12,16")])
+   (set_attr "length" "8,16")])
 
 (define_split
   [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
@@ -11483,7 +11483,7 @@
 		(const_string "mfcrf")
 	   ]
 	(const_string "mfcr")))
-   (set_attr "length" "12")])
+   (set_attr "length" "8")])
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
@@ -11518,7 +11518,7 @@
   return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
 }"
   [(set_attr "type" "delayed_compare")
-   (set_attr "length" "12,16")])
+   (set_attr "length" "8,16")])
 
 (define_split
   [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
@@ -11555,7 +11555,7 @@
   "REGNO (operands[2]) != REGNO (operands[5])"
   "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
   [(set_attr "type" "mfcr")
-   (set_attr "length" "20")])
+   (set_attr "length" "12")])
 
 (define_peephole
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
@@ -11569,7 +11569,7 @@
   "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
   "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
   [(set_attr "type" "mfcr")
-   (set_attr "length" "20")])
+   (set_attr "length" "12")])
 
 ;; There are some scc insns that can be done directly, without a compare.
 ;; These are faster because they don't involve the communications between