Fix PR80082: LDRD erronously used for 64bit load on ARMv7-R

2017-03-22  Thomas Preud'homme  <thomas.preudhomme@arm.com>

    gcc/
    PR target/80082
    * config/arm/arm-isa.h (isa_bit_lpae): New feature bit.
    (ISA_ARMv7ve): Add isa_bit_lpae to the definition.
    * config/arm/arm-protos.h (arm_arch7ve): Rename into ...
    (arm_arch_lpae): This.
    * config/arm/arm.c (arm_arch7ve): Rename into ...
    (arm_arch_lpae): This.  Define it in term of isa_bit_lpae.
    * config/arm/arm.h (TARGET_HAVE_LPAE): Redefine in term of
    arm_arch_lpae.

    gcc/testsuite/
    PR target/80082
    * gcc.target/arm/atomic_loaddi_10.c: New testcase.
    * gcc.target/arm/atomic_loaddi_11.c: Likewise.

From-SVN: r246365

8 files changed, 56 insertions, 8 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 86b6298..18d00c2 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,15 @@
+t2017-03-22  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+	PR target/80082
+	* config/arm/arm-isa.h (isa_bit_lpae): New feature bit.
+	(ISA_ARMv7ve): Add isa_bit_lpae to the definition.
+	* config/arm/arm-protos.h (arm_arch7ve): Rename into ...
+	(arm_arch_lpae): This.
+	* config/arm/arm.c (arm_arch7ve): Rename into ...
+	(arm_arch_lpae): This.  Define it in term of isa_bit_lpae.
+	* config/arm/arm.h (TARGET_HAVE_LPAE): Redefine in term of
+	arm_arch_lpae.
+
 2017-03-22  Martin Liska  <mliska@suse.cz>
 
 	PR target/79906
diff --git a/gcc/config/arm/arm-isa.h b/gcc/config/arm/arm-isa.h
index 6050bca..7d1e23b 100644
--- a/gcc/config/arm/arm-isa.h
+++ b/gcc/config/arm/arm-isa.h
@@ -58,6 +58,7 @@ enum isa_feature
     isa_bit_VFPv3,	/* Vector floating point v3.  */
     isa_bit_VFPv4,	/* Vector floating point v4.  */
     isa_bit_FPv5,	/* Floating point v5.  */
+    isa_bit_lpae,	/* ARMv7-A LPAE.  */
     isa_bit_FP_ARMv8,	/* ARMv8 floating-point extension.  */
     isa_bit_neon,	/* Advanced SIMD instructions.  */
     isa_bit_fp16conv,	/* Conversions to/from fp16 (VFPv3 extension).  */
@@ -116,7 +117,7 @@ enum isa_feature
    integer SIMD instructions that are in ARMv6T2.  */
 #define ISA_ARMv7	ISA_ARMv6m, isa_bit_thumb2, isa_bit_ARMv7
 #define ISA_ARMv7a	ISA_ARMv7, isa_bit_notm, isa_bit_ARMv6k
-#define ISA_ARMv7ve	ISA_ARMv7a, isa_bit_adiv, isa_bit_tdiv
+#define ISA_ARMv7ve	ISA_ARMv7a, isa_bit_adiv, isa_bit_tdiv, isa_bit_lpae
 #define ISA_ARMv7r	ISA_ARMv7a, isa_bit_tdiv
 #define ISA_ARMv7m	ISA_ARMv7, isa_bit_tdiv
 #define ISA_ARMv7em	ISA_ARMv7m, isa_bit_ARMv7em
diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index 680a1e6..cf8b437 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -391,8 +391,8 @@ extern int arm_arch6m;
 /* Nonzero if this chip supports the ARM 7 extensions.  */
 extern int arm_arch7;
 
-/* Nonzero if this chip supports the ARM 7ve extensions.  */
-extern int arm_arch7ve;
+/* Nonzero if this chip supports the Large Physical Address Extension.  */
+extern int arm_arch_lpae;
 
 /* Nonzero if instructions not present in the 'M' profile can be used.  */
 extern int arm_arch_notm;
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 511e163..b24143e 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -841,8 +841,8 @@ int arm_arch6m = 0;
 /* Nonzero if this chip supports the ARM 7 extensions.  */
 int arm_arch7 = 0;
 
-/* Nonzero if this chip supports the ARM 7ve extensions.  */
-int arm_arch7ve = 0;
+/* Nonzero if this chip supports the Large Physical Address Extension.  */
+int arm_arch_lpae = 0;
 
 /* Nonzero if instructions not present in the 'M' profile can be used.  */
 int arm_arch_notm = 0;
@@ -3365,8 +3365,7 @@ arm_option_override (void)
   arm_arch_crc = bitmap_bit_p (arm_active_target.isa, isa_bit_crc32);
   arm_arch_cmse = bitmap_bit_p (arm_active_target.isa, isa_bit_cmse);
   arm_fp16_inst = bitmap_bit_p (arm_active_target.isa, isa_bit_fp16);
-  arm_arch7ve
-    = (arm_arch6k && arm_arch7 && arm_arch_thumb_hwdiv && arm_arch_arm_hwdiv);
+  arm_arch_lpae = bitmap_bit_p (arm_active_target.isa, isa_bit_lpae);
   if (arm_fp16_inst)
     {
       if (arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE)
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index e95eda35..4dab73d 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -251,7 +251,7 @@ extern tree arm_fp16_type_node;
 				  || (arm_arch8 && !arm_arch_notm))
 
 /* Nonzero if this chip supports LPAE.  */
-#define TARGET_HAVE_LPAE (arm_arch7ve)
+#define TARGET_HAVE_LPAE (arm_arch_lpae)
 
 /* Nonzero if this chip supports ldrex{bh} and strex{bh}.  */
 #define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM)		\
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index f7f4a5a..ead24fa 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2017-03-22  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+	PR target/80082
+	* gcc.target/arm/atomic_loaddi_10.c: New testcase.
+	* gcc.target/arm/atomic_loaddi_11.c: Likewise.
+
 2017-03-22  Martin Liska  <mliska@suse.cz>
 
 	PR target/79906
diff --git a/gcc/testsuite/gcc.target/arm/atomic_loaddi_10.c b/gcc/testsuite/gcc.target/arm/atomic_loaddi_10.c
new file mode 100644
index 0000000..ecc3d06
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/atomic_loaddi_10.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_arch_v7ve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_arch_v7ve } */
+
+#include <stdatomic.h>
+
+atomic_llong x = 0;
+
+atomic_llong get_x()
+{
+  return atomic_load(&x);
+}
+
+/* { dg-final { scan-assembler "ldrd" } } */
diff --git a/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c b/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
new file mode 100644
index 0000000..275669b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_arch_v7r_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_arch_v7r } */
+
+#include <stdatomic.h>
+
+atomic_llong x = 0;
+
+atomic_llong get_x()
+{
+  return atomic_load(&x);
+}
+
+/* { dg-final { scan-assembler-not "ldrd" } } */