diff options
| author | Jan Hubicka <jh@suse.cz> | 2007-09-12 09:02:31 +0200 |
|---|---|---|
| committer | Jan Hubicka <hubicka@gcc.gnu.org> | 2007-09-12 07:02:31 +0000 |
| commit | bf019a1f7f992a1feb985c4b656e527475e73a30 (patch) | |
| tree | eda760ba164c77124e8505afebfab187b6c69fb7 /gcc | |
| parent | 926e663ef1ab111abe33fc191f2d09d3082507e8 (diff) | |
| download | gcc-bf019a1f7f992a1feb985c4b656e527475e73a30.zip gcc-bf019a1f7f992a1feb985c4b656e527475e73a30.tar.gz gcc-bf019a1f7f992a1feb985c4b656e527475e73a30.tar.bz2 | |
re PR target/33393 (floatsisf2_sse_vector_nointernunit doesn't work on 32bit)
PR target/33393
* i386.md (floatsisf2_mixed_memory, floatsisf2_sse_memory): Disable for
!SSE_MATH
From-SVN: r128414
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/i386/i386.md | 13 |
2 files changed, 14 insertions, 5 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d25f392..e74a823 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2007-09-12 Jan Hubicka <jh@suse.cz> + + PR target/33393 + * i386.md (floatsisf2_mixed_memory, floatsisf2_sse_memory): Disable for + !SSE_MATH + 2007-09-12 Christian Bruel <christian.bruel@st.com> * sh.h (SH_DBX_REGISTER_NUMBER): Added fpscr, fixed sr/gbr regs. * linux-unwind.h (SH_DWARF_FRAME_GBR): fixed. diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 0c625da..c29f3e3 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -3927,7 +3927,7 @@ [(set (match_operand:DF 0 "register_operand" "") (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))] - "TARGET_USE_VECTOR_CONVERTS && !optimize_size + "(TARGET_USE_VECTOR_CONVERTS || TARGET_GENERIC) && !optimize_size && reload_completed && SSE_REG_P (operands[0])" [(set (match_dup 2) (float_extend:V2DF @@ -4063,7 +4063,7 @@ [(set (match_operand:SF 0 "register_operand" "") (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "")))] - "TARGET_USE_VECTOR_CONVERTS && !optimize_size + "(TARGET_USE_VECTOR_CONVERTS || TARGET_GENERIC) && !optimize_size && reload_completed && SSE_REG_P (operands[0])" [(set (match_dup 2) (vec_concat:V4SF @@ -4876,7 +4876,8 @@ (define_insn "*floatsisf2_sse_vector_nointernunit" [(set (match_operand:SF 0 "register_operand" "=x") (float:SF (match_operand:SI 1 "memory_operand" "m")))] - "flag_trapping_math && TARGET_USE_VECTOR_CONVERTS && !optimize_size + "TARGET_SSE_MATH && flag_trapping_math + && TARGET_USE_VECTOR_CONVERTS && !optimize_size && !TARGET_INTER_UNIT_MOVES" "#" [(set_attr "type" "multi")]) @@ -4884,7 +4885,8 @@ (define_insn "*floatsisf2_sse_vector_internunit" [(set (match_operand:SF 0 "register_operand" "=x,x") (float:SF (match_operand:SI 1 "nonimmediate_operand" "rm,x")))] - "flag_trapping_math && TARGET_USE_VECTOR_CONVERTS && !optimize_size + "TARGET_SSE_MATH && flag_trapping_math + && TARGET_USE_VECTOR_CONVERTS && !optimize_size && TARGET_INTER_UNIT_MOVES" "#" [(set_attr "type" "multi")]) @@ -4921,7 +4923,8 @@ (define_insn "*floatsisf2_sse_vector" [(set (match_operand:SF 0 "register_operand" "=x") (float:SF (match_operand:SI 1 "register_operand" "x")))] - "!flag_trapping_math && TARGET_USE_VECTOR_CONVERTS && !optimize_size + "TARGET_SSE_MATH && !flag_trapping_math + && TARGET_USE_VECTOR_CONVERTS && !optimize_size && !TARGET_INTER_UNIT_MOVES" "cvtdq2ps\t{%1, %0|%0, %1}" [(set_attr "type" "sseicvt") |