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| author | Vladimir N. Makarov <vmakarov@redhat.com> | 2021-03-23 17:51:21 -0400 |
|---|---|---|
| committer | Vladimir N. Makarov <vmakarov@redhat.com> | 2021-03-23 17:58:57 -0400 |
| commit | be70bb5e4babdf9d3d33e8f4658452038407fa8e (patch) | |
| tree | 46984e3fc32cf86314b0570e98f46d528ae8f24d /gcc | |
| parent | e5c2ac584a1d5b7b7f6e77c6c1ddfaaa4165f894 (diff) | |
| download | gcc-be70bb5e4babdf9d3d33e8f4658452038407fa8e.zip gcc-be70bb5e4babdf9d3d33e8f4658452038407fa8e.tar.gz gcc-be70bb5e4babdf9d3d33e8f4658452038407fa8e.tar.bz2 | |
[PR99581] Use relaxed memory for more aarch64 memory constraints
The original patch for PR99581 resulted in GCC testsuite regression as
some constraints were not declared as relaxed memory ones. This patch
fixes this.
gcc/ChangeLog:
PR target/99581
* config/aarch64/constraints.md (Utq, UOb, UOh, UOw, UOd, UOty):
Use define_relaxed_memory_constraint for them.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/aarch64/constraints.md | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constraints.md index f08eea8b..fd3e925 100644 --- a/gcc/config/aarch64/constraints.md +++ b/gcc/config/aarch64/constraints.md @@ -323,7 +323,7 @@ (and (match_code "mem") (match_test "aarch64_simd_mem_operand_p (op)"))) -(define_memory_constraint "Utq" +(define_relaxed_memory_constraint "Utq" "@internal An address valid for loading or storing a 128-bit AdvSIMD register" (and (match_code "mem") @@ -336,32 +336,32 @@ (and (match_code "mem") (match_test "aarch64_sve_ld1rq_operand_p (op)"))) -(define_memory_constraint "UOb" +(define_relaxed_memory_constraint "UOb" "@internal An address valid for SVE LD1ROH." (and (match_code "mem") (match_test "aarch64_sve_ld1ro_operand_p (op, QImode)"))) -(define_memory_constraint "UOh" +(define_relaxed_memory_constraint "UOh" "@internal An address valid for SVE LD1ROH." (and (match_code "mem") (match_test "aarch64_sve_ld1ro_operand_p (op, HImode)"))) -(define_memory_constraint "UOw" +(define_relaxed_memory_constraint "UOw" "@internal An address valid for SVE LD1ROW." (and (match_code "mem") (match_test "aarch64_sve_ld1ro_operand_p (op, SImode)"))) -(define_memory_constraint "UOd" +(define_relaxed_memory_constraint "UOd" "@internal An address valid for SVE LD1ROD." (and (match_code "mem") (match_test "aarch64_sve_ld1ro_operand_p (op, DImode)"))) -(define_memory_constraint "Uty" +(define_relaxed_memory_constraint "Uty" "@internal An address valid for SVE LD1Rs." (and (match_code "mem") |