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| author | Ian Bolton <ian.bolton@arm.com> | 2013-03-19 16:17:14 +0000 |
|---|---|---|
| committer | Ian Bolton <ibolton@gcc.gnu.org> | 2013-03-19 16:17:14 +0000 |
| commit | bd83ff2c6700863b92c59931c4ba4a1bef97a50f (patch) | |
| tree | 98f69a52b1e2129b81bdfa73e10e58d4699395ca /gcc | |
| parent | ba65123cbe4253a503e64818d92fe02848f57544 (diff) | |
| download | gcc-bd83ff2c6700863b92c59931c4ba4a1bef97a50f.zip gcc-bd83ff2c6700863b92c59931c4ba4a1bef97a50f.tar.gz gcc-bd83ff2c6700863b92c59931c4ba4a1bef97a50f.tar.bz2 | |
AArch64 backend support for EXTR instruction.
From-SVN: r196795
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 28 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 4 |
3 files changed, 37 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b55bc7f..4b2d216 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2013-03-19 Ian Bolton <ian.bolton@arm.com> + + * config/aarch64/aarch64.md (*extr<mode>5_insn): New pattern. + (*extrsi5_insn_uxtw): Likewise. + 2013-03-19 Richard Biener <rguenther@suse.de> PR tree-optimization/56273 diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 76a5125..8fc86d4 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -2703,6 +2703,34 @@ (set_attr "mode" "<MODE>")] ) +(define_insn "*extr<mode>5_insn" + [(set (match_operand:GPI 0 "register_operand" "=r") + (ior:GPI (ashift:GPI (match_operand:GPI 1 "register_operand" "r") + (match_operand 3 "const_int_operand" "n")) + (lshiftrt:GPI (match_operand:GPI 2 "register_operand" "r") + (match_operand 4 "const_int_operand" "n"))))] + "UINTVAL (operands[3]) < GET_MODE_BITSIZE (<MODE>mode) && + (UINTVAL (operands[3]) + UINTVAL (operands[4]) == GET_MODE_BITSIZE (<MODE>mode))" + "extr\\t%<w>0, %<w>1, %<w>2, %4" + [(set_attr "v8type" "shift") + (set_attr "mode" "<MODE>")] +) + +;; zero_extend version of the above +(define_insn "*extrsi5_insn_uxtw" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI + (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r") + (match_operand 3 "const_int_operand" "n")) + (lshiftrt:SI (match_operand:SI 2 "register_operand" "r") + (match_operand 4 "const_int_operand" "n")))))] + "UINTVAL (operands[3]) < 32 && + (UINTVAL (operands[3]) + UINTVAL (operands[4]) == 32)" + "extr\\t%w0, %w1, %w2, %4" + [(set_attr "v8type" "shift") + (set_attr "mode" "SI")] +) + (define_insn "*<ANY_EXTEND:optab><GPI:mode>_ashl<SHORT:mode>" [(set (match_operand:GPI 0 "register_operand" "=r") (ANY_EXTEND:GPI diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 5a65528..fa69025 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2013-03-19 Ian Bolton <ian.bolton@arm.com> + + * gcc.target/aarch64/extr.c: New test. + 2013-03-19 Richard Biener <rguenther@suse.de> PR tree-optimization/56273 |