re PR target/39079 (MIPS: __builtin___clear_cache() broken on SMP ISA_HAS_SYNCI systems.)

2009-07-10  David Daney  <ddaney@caviumnetworks.com>

	PR target/39079
	* testsuite/gcc.target/mips/mips.exp: Make -msynci a known option.
	* gcc.target/mips/clear-cache-1.c (dg-options): Add -msynci.

2009-07-10  David Daney  <ddaney@caviumnetworks.com>

	PR target/39079
	* config.gcc (supported_defaults): Add synci.
	(with_synci): Add validation.
	(all_defaults): Add synci.
	* config/mips/mips.md (clear_cache): Use TARGET_SYNCI instead of
	ISA_HAS_SYNCI.
	(synci): Same.
	* config/mips/mips.opt (msynci): New option.
	* config/mips/mips.c (mips_override_options): Warn on use of
	-msynci for targets that do now support it.
	* gcc/config/mips/mips.h (OPTION_DEFAULT_SPECS): Add a default for
	msynci.
	* gcc/doc/invoke.texi (-msynci): Document the new option.
	* doc/install.texi (--with-synci): Document the new option.

From-SVN: r149500

11 files changed, 81 insertions, 7 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 684b6cd..bff4bd7 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,20 @@
+2009-07-10  David Daney  <ddaney@caviumnetworks.com>
+
+	PR target/39079
+	* config.gcc (supported_defaults): Add synci.
+	(with_synci): Add validation.
+	(all_defaults): Add synci.
+	* config/mips/mips.md (clear_cache): Use TARGET_SYNCI instead of
+	ISA_HAS_SYNCI.
+	(synci): Same.
+	* config/mips/mips.opt (msynci): New option.
+	* config/mips/mips.c (mips_override_options): Warn on use of
+	-msynci for targets that do now support it.
+	* gcc/config/mips/mips.h (OPTION_DEFAULT_SPECS): Add a default for
+	msynci.
+	* gcc/doc/invoke.texi (-msynci): Document the new option.
+	* doc/install.texi (--with-synci): Document the new option.
+
 2009-07-10  Richard Guenther  <rguenther@suse.de>
 
 	PR tree-optimization/40496
diff --git a/gcc/config.gcc b/gcc/config.gcc
index fe345c1..98d7771 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -2902,7 +2902,7 @@ case "${target}" in
 		;;
 
 	mips*-*-*)
-		supported_defaults="abi arch arch_32 arch_64 float tune tune_32 tune_64 divide llsc mips-plt"
+		supported_defaults="abi arch arch_32 arch_64 float tune tune_32 tune_64 divide llsc mips-plt synci"
 
 		case ${with_float} in
 		"" | soft | hard)
@@ -2964,6 +2964,20 @@ case "${target}" in
 			exit 1
 			;;
 		esac
+
+		case ${with_synci} in
+		yes)
+			with_synci=synci
+			;;
+		"" | no)
+			# No is the default.
+			with_synci=no-synci
+			;;
+		*)
+			echo "Unknown synci type used in --with-synci" 1>&2
+			exit 1
+			;;
+		esac
 		;;
 
 	powerpc*-*-* | rs6000-*-*)
@@ -3230,7 +3244,7 @@ case ${target} in
 esac
 
 t=
-all_defaults="abi cpu cpu_32 cpu_64 arch arch_32 arch_64 tune tune_32 tune_64 schedule float mode fpu divide llsc mips-plt"
+all_defaults="abi cpu cpu_32 cpu_64 arch arch_32 arch_64 tune tune_32 tune_64 schedule float mode fpu divide llsc mips-plt synci"
 for option in $all_defaults
 do
 	eval "val=\$with_"`echo $option | sed s/-/_/g`
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 3615892..4a10fb4 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -14524,6 +14524,13 @@ mips_override_options (void)
           : !TARGET_BRANCHLIKELY))
     sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
 
+  if (TARGET_SYNCI && !ISA_HAS_SYNCI)
+    {
+      warning (0, "the %qs architecture does not support the synci "
+	       "instruction", mips_arch_info->name);
+      target_flags &= ~MASK_SYNCI;
+    }
+
   /* Save base state of options.  */
   mips_base_target_flags = target_flags;
   mips_base_schedule_insns = flag_schedule_insns;
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index c8ea605..a3ab2f8 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -787,7 +787,8 @@ enum mips_code_readable_setting {
   {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
   {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
   {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
-  {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }
+  {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
+  {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }
 
 
 /* A spec that infers the -mdsp setting from an -march argument.  */
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 46e7afa..3c42b46 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -4728,7 +4728,7 @@
   ""
   "
 {
-  if (ISA_HAS_SYNCI)
+  if (TARGET_SYNCI)
     {
       mips_expand_synci_loop (operands[0], operands[1]);
       emit_insn (gen_sync ());
@@ -4753,7 +4753,7 @@
 (define_insn "synci"
   [(unspec_volatile [(match_operand 0 "pmode_register_operand" "d")]
 		    UNSPEC_SYNCI)]
-  "ISA_HAS_SYNCI"
+  "TARGET_SYNCI"
   "synci\t0(%0)")
 
 (define_insn "rdhwr_synci_step_<mode>"
diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt
index 9016754..9038125 100644
--- a/gcc/config/mips/mips.opt
+++ b/gcc/config/mips/mips.opt
@@ -268,6 +268,10 @@ msym32
 Target Report Var(TARGET_SYM32)
 Assume all symbols have 32-bit values
 
+msynci
+Target Report Mask(SYNCI)
+Use synci instruction to invalidate i-cache
+
 mtune=
 Target RejectNegative Joined Var(mips_tune_string)
 -mtune=PROCESSOR	Optimize the output for PROCESSOR
diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi
index 0679459..a480dc5 100644
--- a/gcc/doc/install.texi
+++ b/gcc/doc/install.texi
@@ -1170,6 +1170,14 @@ not provide them.
 On MIPS targets, make @option{-mno-llsc} the default when no
 @option{-mllsc} option is passed.
 
+@item --with-synci
+On MIPS targets, make @option{-msynci} the default when no
+@option{-mno-synci} option is passed.
+
+@item --without-synci 
+On MIPS targets, make @option{-mno-synci} the default when no
+@option{-msynci} option is passed.  This is the default.
+
 @item --with-mips-plt
 On MIPS targets, make use of copy relocations and PLTs.
 These features are extensions to the traditional
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index cb51dfb..b831395 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -695,7 +695,7 @@ Objective-C and Objective-C++ Dialects}.
 -mflush-func=@var{func}  -mno-flush-func @gol
 -mbranch-cost=@var{num}  -mbranch-likely  -mno-branch-likely @gol
 -mfp-exceptions -mno-fp-exceptions @gol
--mvr4130-align -mno-vr4130-align}
+-mvr4130-align -mno-vr4130-align -msynci -mno-synci}
 
 @emph{MMIX Options}
 @gccoptlist{-mlibfuncs  -mno-libfuncs  -mepsilon  -mno-epsilon  -mabi=gnu @gol
@@ -13712,6 +13712,22 @@ thinks should execute in parallel.
 This option only has an effect when optimizing for the VR4130.
 It normally makes code faster, but at the expense of making it bigger.
 It is enabled by default at optimization level @option{-O3}.
+
+@item -msynci
+@itemx -mno-synci
+@opindex msynci
+Enable (disable) generation of @code{synci} instructions on
+architectures that support it.  The @code{synci} instructions (if
+enabled) will be generated when @code{__builtin___clear_cache()} is
+compiled.
+
+This option defaults to @code{-mno-synci}, but the default can be
+overridden by configuring with @code{--with-synci}.
+
+When compiling code for single processor systems, it is generally safe
+to use @code{synci}.  However, on many multi-core (SMP) systems, it
+will not invalidate the instruction caches on all cores and may lead
+to undefined behavior.
 @end table
 
 @node MMIX Options
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 7e7be11..6a873c7 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2009-07-10  David Daney  <ddaney@caviumnetworks.com>
+
+	PR target/39079
+	* testsuite/gcc.target/mips/mips.exp: Make -msynci a known option.
+	* gcc.target/mips/clear-cache-1.c (dg-options): Add -msynci.
+
 2009-07-10  Jakub Jelinek  <jakub@redhat.com>
 
 	PR c++/40502
diff --git a/gcc/testsuite/gcc.target/mips/clear-cache-1.c b/gcc/testsuite/gcc.target/mips/clear-cache-1.c
index 60bbf9d..0ccc007 100644
--- a/gcc/testsuite/gcc.target/mips/clear-cache-1.c
+++ b/gcc/testsuite/gcc.target/mips/clear-cache-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 isa_rev>=2" } */
+/* { dg-options "-O2 -msynci isa_rev>=2" } */
 /* { dg-final { scan-assembler "synci" } } */
 /* { dg-final { scan-assembler "jr.hb" } } */
 /* { dg-final { scan-assembler-not "_flush_cache" } } */
diff --git a/gcc/testsuite/gcc.target/mips/mips.exp b/gcc/testsuite/gcc.target/mips/mips.exp
index a0b8fc3..5ec2142 100644
--- a/gcc/testsuite/gcc.target/mips/mips.exp
+++ b/gcc/testsuite/gcc.target/mips/mips.exp
@@ -234,6 +234,7 @@ foreach option {
     shared
     smartmips
     sym32
+    synci
 } {
     lappend mips_option_groups $option "-m(no-|)$option"
 }