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| author | Patrick O'Neill <patrick@rivosinc.com> | 2023-04-07 15:14:17 -0700 |
|---|---|---|
| committer | Patrick O'Neill <patrick@rivosinc.com> | 2023-05-02 13:08:04 -0700 |
| commit | b90e030a3cef2158579618ad883783170ef58fa0 (patch) | |
| tree | 776113e5d170ba4a180c76c2a4063b8e4d6ac4ee /gcc | |
| parent | bff7c77386447936dd614ebc7086b826c99c6642 (diff) | |
| download | gcc-b90e030a3cef2158579618ad883783170ef58fa0.zip gcc-b90e030a3cef2158579618ad883783170ef58fa0.tar.gz gcc-b90e030a3cef2158579618ad883783170ef58fa0.tar.bz2 | |
RISC-V: Weaken atomic loads
This change brings atomic loads in line with table A.6 of the ISA
manual.
2023-04-27 Patrick O'Neill <patrick@rivosinc.com>
gcc/ChangeLog:
* config/riscv/sync.md (atomic_load<mode>): Implement atomic
load mapping.
Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/riscv/sync.md | 28 |
1 files changed, 26 insertions, 2 deletions
diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index ba132d8..6e7c762 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -26,6 +26,7 @@ UNSPEC_SYNC_OLD_OP_SUBWORD UNSPEC_SYNC_EXCHANGE UNSPEC_SYNC_EXCHANGE_SUBWORD + UNSPEC_ATOMIC_LOAD UNSPEC_ATOMIC_STORE UNSPEC_MEMORY_BARRIER ]) @@ -66,8 +67,31 @@ ;; Atomic memory operations. -;; Implement atomic stores with conservative fences. Fall back to fences for -;; atomic loads. +(define_insn "atomic_load<mode>" + [(set (match_operand:GPR 0 "register_operand" "=r") + (unspec_volatile:GPR + [(match_operand:GPR 1 "memory_operand" "A") + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPEC_ATOMIC_LOAD))] + "TARGET_ATOMIC" + { + enum memmodel model = (enum memmodel) INTVAL (operands[2]); + model = memmodel_base (model); + + if (model == MEMMODEL_SEQ_CST) + return "fence\trw,rw\;" + "l<amo>\t%0,%1\;" + "fence\tr,rw"; + if (model == MEMMODEL_ACQUIRE) + return "l<amo>\t%0,%1\;" + "fence\tr,rw"; + else + return "l<amo>\t%0,%1"; + } + [(set_attr "type" "atomic") + (set (attr "length") (const_int 12))]) + +;; Implement atomic stores with conservative fences. ;; This allows us to be compatible with the ISA manual Table A.6 and Table A.7. (define_insn "atomic_store<mode>" [(set (match_operand:GPR 0 "memory_operand" "=A") |