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| author | Jim Wilson <jimw@sifive.com> | 2020-02-08 13:57:36 -0800 |
|---|---|---|
| committer | Jim Wilson <jimw@sifive.com> | 2020-02-08 13:57:36 -0800 |
| commit | b780f68e025b2cf5631183e199ebf672ea463af6 (patch) | |
| tree | b9ec58ed666f0e5c8b6f3684cedb66b57a108aa6 /gcc | |
| parent | aaa26bf496a646778ac861aed124d960b5bf549f (diff) | |
| download | gcc-b780f68e025b2cf5631183e199ebf672ea463af6.zip gcc-b780f68e025b2cf5631183e199ebf672ea463af6.tar.gz gcc-b780f68e025b2cf5631183e199ebf672ea463af6.tar.bz2 | |
RISC-V: Improve caller-save code generation.
Avoid paradoxical subregs when caller save. This reduces stack frame size
due to smaller loads and stores, and more frequent rematerialization.
PR target/93532
* config/riscv/riscv.h (HARD_REGNO_CALLER_SAVE_MODE): Define.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/riscv/riscv.h | 7 |
2 files changed, 12 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ed3aac4..0ae8c54 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2020-02-08 Jim Wilson <jimw@sifive.com> + + PR target/93532 + * config/riscv/riscv.h (HARD_REGNO_CALLER_SAVE_MODE): Define. + 2020-02-08 Uroš Bizjak <ubizjak@gmail.com> Jakub Jelinek <jakub@redhat.com> diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 19438e2..567c233 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -268,6 +268,13 @@ along with GCC; see the file COPYING3. If not see 1, 1 \ } +/* Select a register mode required for caller save of hard regno REGNO. + Contrary to what is documented, the default is not the smallest suitable + mode but the largest suitable mode for the given (REGNO, NREGS) pair and + it quickly creates paradoxical subregs that can be problematic. */ +#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ + ((MODE) == VOIDmode ? choose_hard_reg_mode (REGNO, NREGS, NULL) : (MODE)) + /* Internal macros to classify an ISA register's type. */ #define GP_REG_FIRST 0 |