diff options
| author | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2022-08-12 16:29:10 +0100 |
|---|---|---|
| committer | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2022-08-12 16:31:13 +0100 |
| commit | b748d46ab15f5e745437af0653329059f9b35669 (patch) | |
| tree | 136ebeec9ef00923e2c16afec0be7d8103b05086 /gcc | |
| parent | 0f2c7ccd14a29a8af8318f50b8296098fb0ab218 (diff) | |
| download | gcc-b748d46ab15f5e745437af0653329059f9b35669.zip gcc-b748d46ab15f5e745437af0653329059f9b35669.tar.gz gcc-b748d46ab15f5e745437af0653329059f9b35669.tar.bz2 | |
[Committed] arm: Document +no options for Cortex-M55 CPU.
This patch documents the following options for Arm Cortex-M55 CPU
under -mcpu= list.
+nomve.fp (disables MVE single precision floating point instructions)
+nomve (disables MVE integer and single precision floating point instructions)
+nodsp (disables dsp, MVE integer and single precision floating point instructions)
+nofp (disables floating point instructions)
Committed as obvious to master.
gcc/ChangeLog:
2022-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* doc/invoke.texi (Arm Options): Document -mcpu=cortex-m55 options.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/doc/invoke.texi | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 3b529c4..b264ae2 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -21638,14 +21638,25 @@ The following extension options are common to the listed CPUs: @table @samp @item +nodsp -Disable the DSP instructions on @samp{cortex-m33}, @samp{cortex-m35p}. +Disable the DSP instructions on @samp{cortex-m33}, @samp{cortex-m35p} +and @samp{cortex-m55}. Also disable the M-Profile Vector Extension (MVE) +integer and single precision floating-point instructions on @samp{cortex-m55}. + +@item +nomve +Disable the M-Profile Vector Extension (MVE) integer and single precision +floating-point instructions on @samp{cortex-m55}. + +@item +nomve.fp +Disable the M-Profile Vector Extension (MVE) single precision floating-point +instructions on @samp{cortex-m55}. @item +nofp Disables the floating-point instructions on @samp{arm9e}, @samp{arm946e-s}, @samp{arm966e-s}, @samp{arm968e-s}, @samp{arm10e}, @samp{arm1020e}, @samp{arm1022e}, @samp{arm926ej-s}, @samp{arm1026ej-s}, @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-r8}, -@samp{cortex-m4}, @samp{cortex-m7}, @samp{cortex-m33} and @samp{cortex-m35p}. +@samp{cortex-m4}, @samp{cortex-m7}, @samp{cortex-m33}, @samp{cortex-m35p} +and @samp{cortex-m55}. Disables the floating-point and SIMD instructions on @samp{generic-armv7-a}, @samp{cortex-a5}, @samp{cortex-a7}, @samp{cortex-a8}, @samp{cortex-a9}, @samp{cortex-a12}, |