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| author | liuhongt <hongtao.liu@intel.com> | 2023-03-31 14:52:51 +0800 |
|---|---|---|
| committer | liuhongt <hongtao.liu@intel.com> | 2023-04-03 09:17:42 +0800 |
| commit | b551ea379947c640358c9f20f71c5c6237d85d0f (patch) | |
| tree | e65129ed13f9e6176d8eed570cc1dfaf4aa0cffa /gcc | |
| parent | 5f10c7f2d8513d9f638108edfd1b7ed16de8b1a0 (diff) | |
| download | gcc-b551ea379947c640358c9f20f71c5c6237d85d0f.zip gcc-b551ea379947c640358c9f20f71c5c6237d85d0f.tar.gz gcc-b551ea379947c640358c9f20f71c5c6237d85d0f.tar.bz2 | |
Document signbitm2.
gcc/ChangeLog:
* doc/md.texi: Document signbitm2.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/doc/md.texi | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 8e31135..edfa51e 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -6030,6 +6030,17 @@ floating-point mode. This pattern is not allowed to @code{FAIL}. +@cindex @code{signbit@var{m}2} instruction pattern +@item @samp{signbit@var{m}2} +Store the sign bit of floating-point operand 1 in operand 0. +@var{m} is either a scalar or vector mode. When it is a scalar, +operand 1 has mode @var{m} but operand 0 must have mode @code{SImode}. +When @var{m} is a vector, operand 1 has the mode @var{m}. +operand 0's mode should be an vector integer mode which has +the same number of elements and the same size as mode @var{m}. + +This pattern is not allowed to @code{FAIL}. + @cindex @code{significand@var{m}2} instruction pattern @item @samp{significand@var{m}2} Store the significand of floating-point operand 1 in operand 0. |