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| author | xuli <xuli1@eswincomputing.com> | 2023-10-24 07:39:02 +0000 |
|---|---|---|
| committer | xuli <xuli1@eswincomputing.com> | 2023-10-24 07:47:52 +0000 |
| commit | b44d4ff7b43ff6a34d5c074c7ade03c4a38974fa (patch) | |
| tree | 9e2c554c5e0c3e9681ba92859888a8a00d70f6cc /gcc | |
| parent | eaf75155f38a51b2d9d49c6c1b1e1639e3d0591a (diff) | |
| download | gcc-b44d4ff7b43ff6a34d5c074c7ade03c4a38974fa.zip gcc-b44d4ff7b43ff6a34d5c074c7ade03c4a38974fa.tar.gz gcc-b44d4ff7b43ff6a34d5c074c7ade03c4a38974fa.tar.bz2 | |
RISC-V: Fix ICE of RVV vget/vset intrinsic[PR111935]
Calling vget/vset intrinsic without receiving a return value will cause
a crash. Because in this case e.target is null.
This patch should be backported to releases/gcc-13.
PR target/111935
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc: fix bug.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr111935.c: New test.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/riscv/riscv-vector-builtins-bases.cc | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/base/pr111935.c | 26 |
2 files changed, 30 insertions, 0 deletions
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index ab12e13..0b1409a 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -1740,6 +1740,8 @@ public: rtx expand (function_expander &e) const override { + if (!e.target) + return NULL_RTX; rtx dest = expand_normal (CALL_EXPR_ARG (e.exp, 0)); gcc_assert (riscv_v_ext_vector_mode_p (GET_MODE (dest))); rtx index = expand_normal (CALL_EXPR_ARG (e.exp, 1)); @@ -1777,6 +1779,8 @@ public: rtx expand (function_expander &e) const override { + if (!e.target) + return NULL_RTX; rtx src = expand_normal (CALL_EXPR_ARG (e.exp, 0)); gcc_assert (riscv_v_ext_vector_mode_p (GET_MODE (src))); rtx index = expand_normal (CALL_EXPR_ARG (e.exp, 1)); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111935.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111935.c new file mode 100644 index 0000000..0b936d8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111935.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O0 -Wno-psabi" } */ + +#include "riscv_vector.h" + +inline vuint32m4_t __attribute__((__always_inline__)) transpose_indexes() { + static const uint32_t idx_[16] = {0, 4, 8, 12, + 1, 5, 9, 13, + 2, 6, 10, 14, + 3, 7, 11, 15}; + return __riscv_vle32_v_u32m4(idx_, 16); +} + +void pffft_real_preprocess_4x4(const float *in) { + vfloat32m1_t r0=__riscv_vle32_v_f32m1(in,4); + vfloat32m4_t tmp = __riscv_vundefined_f32m4(); + tmp = __riscv_vset_v_f32m1_f32m4(tmp, 0, r0); + tmp = __riscv_vset_v_f32m1_f32m4(tmp, 1, r0); + tmp = __riscv_vset_v_f32m1_f32m4(tmp, 2, r0); + tmp = __riscv_vset_v_f32m1_f32m4(tmp, 3, r0); + tmp = __riscv_vrgather_vv_f32m4(tmp, transpose_indexes(), 16); + r0 = __riscv_vget_v_f32m4_f32m1(tmp, 0); +} + +/* { dg-final { scan-assembler-times {vl[0-9]+re[0-9]+\.v\s+v[0-9]+,\s*0\([a-z]+[0-9]+\)} 10 } } */ +/* { dg-final { scan-assembler-times {vs[0-9]+r\.v\s+v[0-9]+,\s*0\([a-z]+[0-9]+\)} 8 } } */ |