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| author | Alan Lawrence <alan.lawrence@arm.com> | 2015-09-15 12:48:15 +0000 |
|---|---|---|
| committer | Alan Lawrence <alalaw01@gcc.gnu.org> | 2015-09-15 12:48:15 +0000 |
| commit | abf47511f57721e791c48852c01bb32d0689525f (patch) | |
| tree | 6ff19dd9544108f7c200c53d3cd507370f512eb7 /gcc | |
| parent | d866f024fd0960e8a3629d18d6168709623efb82 (diff) | |
| download | gcc-abf47511f57721e791c48852c01bb32d0689525f.zip gcc-abf47511f57721e791c48852c01bb32d0689525f.tar.gz gcc-abf47511f57721e791c48852c01bb32d0689525f.tar.bz2 | |
[AArch64 array_mode 6/8] Remove V_TWO_ELEM, again using BLKmode + set_mem_size.
* config/aarch64/aarch64-simd.md (aarch64_simd_ld2r<mode>):
Change operand mode from <V_TWO_ELEM> to BLK.
(aarch64_vec_load_lanesoi_lane<mode>): Likewise.
(aarch64_vec_store_lanesoi_lane<mode): Likewise
(aarch64_ld2r<mode>): Generate MEM rtx with BLKmode, call set_mem_size.
(aarch64_ld2_lane<mode>): Likewise.
(aarch64_st2_lane<VQ:mode>): Likewise.
* config/aarch64/iterators.md (V_TWO_ELEM): Remove.
From-SVN: r227790
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 11 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 20 | ||||
| -rw-r--r-- | gcc/config/aarch64/iterators.md | 10 |
3 files changed, 21 insertions, 20 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9ba71fe..c1c2c5f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,16 @@ 2015-09-15 Alan Lawrence <alan.lawrence@arm.com> + * config/aarch64/aarch64-simd.md (aarch64_simd_ld2r<mode>): + Change operand mode from <V_TWO_ELEM> to BLK. + (aarch64_vec_load_lanesoi_lane<mode>): Likewise. + (aarch64_vec_store_lanesoi_lane<mode): Likewise + (aarch64_ld2r<mode>): Generate MEM rtx with BLKmode, call set_mem_size. + (aarch64_ld2_lane<mode>): Likewise. + (aarch64_st2_lane<VQ:mode>): Likewise. + * config/aarch64/iterators.md (V_TWO_ELEM): Remove. + +2015-09-15 Alan Lawrence <alan.lawrence@arm.com> + * config/aarch64/aarch64-simd.md (aarch64_simd_ld4r<mode>): Change operand mode from <V_FOUR_ELEM> to BLK. (aarch64_vec_load_lanesxi_lane<mode>): Likewise. diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 11b5ded..f239ee7 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -3928,7 +3928,7 @@ (define_insn "aarch64_simd_ld2r<mode>" [(set (match_operand:OI 0 "register_operand" "=w") - (unspec:OI [(match_operand:<V_TWO_ELEM> 1 "aarch64_simd_struct_operand" "Utv") + (unspec:OI [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv") (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) ] UNSPEC_LD2_DUP))] "TARGET_SIMD" @@ -3938,7 +3938,7 @@ (define_insn "aarch64_vec_load_lanesoi_lane<mode>" [(set (match_operand:OI 0 "register_operand" "=w") - (unspec:OI [(match_operand:<V_TWO_ELEM> 1 "aarch64_simd_struct_operand" "Utv") + (unspec:OI [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv") (match_operand:OI 2 "register_operand" "0") (match_operand:SI 3 "immediate_operand" "i") (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) ] @@ -3982,8 +3982,8 @@ ;; RTL uses GCC vector extension indices, so flip only for assembly. (define_insn "aarch64_vec_store_lanesoi_lane<mode>" - [(set (match_operand:<V_TWO_ELEM> 0 "aarch64_simd_struct_operand" "=Utv") - (unspec:<V_TWO_ELEM> [(match_operand:OI 1 "register_operand" "w") + [(set (match_operand:BLK 0 "aarch64_simd_struct_operand" "=Utv") + (unspec:BLK [(match_operand:OI 1 "register_operand" "w") (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) (match_operand:SI 2 "immediate_operand" "i")] UNSPEC_ST2_LANE))] @@ -4387,8 +4387,8 @@ (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] "TARGET_SIMD" { - machine_mode mode = <V_TWO_ELEM>mode; - rtx mem = gen_rtx_MEM (mode, operands[1]); + rtx mem = gen_rtx_MEM (BLKmode, operands[1]); + set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) * 2); emit_insn (gen_aarch64_simd_ld2r<mode> (operands[0], mem)); DONE; @@ -4607,8 +4607,8 @@ (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] "TARGET_SIMD" { - machine_mode mode = <V_TWO_ELEM>mode; - rtx mem = gen_rtx_MEM (mode, operands[1]); + rtx mem = gen_rtx_MEM (BLKmode, operands[1]); + set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) * 2); emit_insn (gen_aarch64_vec_load_lanesoi_lane<mode> (operands[0], mem, @@ -4889,8 +4889,8 @@ (match_operand:SI 2 "immediate_operand")] "TARGET_SIMD" { - machine_mode mode = <V_TWO_ELEM>mode; - rtx mem = gen_rtx_MEM (mode, operands[0]); + rtx mem = gen_rtx_MEM (BLKmode, operands[0]); + set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) * 2); emit_insn (gen_aarch64_vec_store_lanesoi_lane<mode> (mem, operands[1], diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index c91b354..aab164a 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -594,16 +594,6 @@ (V2SI "V16SI") (V2SF "V16SF") (DI "V8DI") (DF "V8DF")]) -;; Mode of pair of elements for each vector mode, to define transfer -;; size for structure lane/dup loads and stores. -(define_mode_attr V_TWO_ELEM [(V8QI "HI") (V16QI "HI") - (V4HI "SI") (V8HI "SI") - (V2SI "V2SI") (V4SI "V2SI") - (DI "V2DI") (V2DI "V2DI") - (V2SF "V2SF") (V4SF "V2SF") - (V4HF "SF") (V8HF "SF") - (DF "V2DI") (V2DF "V2DI")]) - ;; Mode for atomic operation suffixes (define_mode_attr atomic_sfx [(QI "b") (HI "h") (SI "") (DI "")]) |