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| author | Pan Li <pan2.li@intel.com> | 2023-10-07 12:39:14 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-10-07 12:57:12 +0800 |
| commit | a809a556dc0792a34fca7b754ff96ea3ea7d1e7f (patch) | |
| tree | f072e42528d839f138e82460f48c647697a5771e /gcc | |
| parent | 15c1530ebbbcff5ddd254988904c5d5ce72c58f4 (diff) | |
| download | gcc-a809a556dc0792a34fca7b754ff96ea3ea7d1e7f.zip gcc-a809a556dc0792a34fca7b754ff96ea3ea7d1e7f.tar.gz gcc-a809a556dc0792a34fca7b754ff96ea3ea7d1e7f.tar.bz2 | |
RISC-V: Bugfix for legitimize address PR/111634
Given we have RTL as below.
(plus:DI (mult:DI (reg:DI 138 [ g.4_6 ])
(const_int 8 [0x8]))
(lo_sum:DI (reg:DI 167)
(symbol_ref:DI ("f") [flags 0x86] <var_decl 0x7fa96ea1cc60 f>)
))
When handling (plus (plus (mult (a) (mem_shadd_constant)) (fp)) (C)) case,
the fp will be the lo_sum operand as above. We have assumption that the fp
is reg but actually not here. It will have ICE when building with option
--enable-checking=rtl.
This patch would like to fix it by adding the REG_P to ensure the operand
is a register. The test case gcc/testsuite/gcc.dg/pr109417.c covered this
fix when build with --enable-checking=rtl.
PR target/111634
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_legitimize_address): Ensure
object is a REG before extracting its' REGNO.
Signed-off-by: Pan Li <pan2.li@intel.com>
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/riscv/riscv.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index d5446b6..2b83924 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -2042,7 +2042,7 @@ riscv_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, { rtx index = XEXP (base, 0); rtx fp = XEXP (base, 1); - if (REGNO (fp) == VIRTUAL_STACK_VARS_REGNUM) + if (REG_P (fp) && REGNO (fp) == VIRTUAL_STACK_VARS_REGNUM) { /* If we were given a MULT, we must fix the constant |