diff options
| author | Patrick O'Neill <patrick@rivosinc.com> | 2023-04-05 09:47:05 -0700 |
|---|---|---|
| committer | Patrick O'Neill <patrick@rivosinc.com> | 2023-05-02 13:08:03 -0700 |
| commit | a61a067b15221de981afd4df8433e96a8cf32341 (patch) | |
| tree | 3aa764b6b0961eb8f7b3a438ffc81d1c1ad292f6 /gcc | |
| parent | d199d2e56da2379004e7e0457150409c0c99d3e6 (diff) | |
| download | gcc-a61a067b15221de981afd4df8433e96a8cf32341.zip gcc-a61a067b15221de981afd4df8433e96a8cf32341.tar.gz gcc-a61a067b15221de981afd4df8433e96a8cf32341.tar.bz2 | |
RISC-V: Add AMO release bits
This patch sets the relevant .rl bits on amo operations.
2023-04-27 Patrick O'Neill <patrick@rivosinc.com>
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_print_operand): Change behavior
of %A to include release bits.
Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/riscv/riscv.cc | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 11af780..f8bc402 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -4508,8 +4508,13 @@ riscv_print_operand (FILE *file, rtx op, int letter) break; case 'A': - if (riscv_memmodel_needs_amo_acquire (model)) + if (riscv_memmodel_needs_amo_acquire (model) + && riscv_memmodel_needs_release_fence (model)) + fputs (".aqrl", file); + else if (riscv_memmodel_needs_amo_acquire (model)) fputs (".aq", file); + else if (riscv_memmodel_needs_release_fence (model)) + fputs (".rl", file); break; case 'F': |