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| author | Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> | 2023-01-18 14:43:13 +0900 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2023-01-18 02:28:13 -0800 |
| commit | a4b05944b7d409682197a9f50759a4ed97145e23 (patch) | |
| tree | 694953f34faa42de6085f0043ca3f05cc364570a /gcc | |
| parent | aaf29ae6cdbaad58b709a77784375d15138174b3 (diff) | |
| download | gcc-a4b05944b7d409682197a9f50759a4ed97145e23.zip gcc-a4b05944b7d409682197a9f50759a4ed97145e23.tar.gz gcc-a4b05944b7d409682197a9f50759a4ed97145e23.tar.bz2 | |
xtensa: Optimize inversion of the MSB
Such operation can be done either bitwise-XOR or addition with -2147483648,
but the latter is one byte less if TARGET_DENSITY.
gcc/ChangeLog:
* config/xtensa/xtensa.md (xorsi3_internal):
Rename from the original of "xorsi3".
(xorsi3): New expansion pattern that emits addition rather than
bitwise-XOR when the second source is a constant of -2147483648
if TARGET_DENSITY.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/xtensa/xtensa.md | 26 |
1 files changed, 25 insertions, 1 deletions
diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md index 98f3c46..dd3fc37 100644 --- a/gcc/config/xtensa/xtensa.md +++ b/gcc/config/xtensa/xtensa.md @@ -736,7 +736,31 @@ (set_attr "mode" "SI") (set_attr "length" "3")]) -(define_insn "xorsi3" +(define_expand "xorsi3" + [(set (match_operand:SI 0 "register_operand") + (xor:SI (match_operand:SI 1 "register_operand") + (match_operand:SI 2 "nonmemory_operand")))] + "" +{ + if (register_operand (operands[2], SImode)) + emit_insn (gen_xorsi3_internal (operands[0], operands[1], + operands[2])); + else + { + rtx (*gen_op)(rtx, rtx, rtx); + if (TARGET_DENSITY + && CONST_INT_P (operands[2]) + && INTVAL (operands[2]) == -2147483648L) + gen_op = gen_addsi3; + else + gen_op = gen_xorsi3_internal; + emit_insn (gen_op (operands[0], operands[1], + force_reg (SImode, operands[2]))); + } + DONE; +}) + +(define_insn "xorsi3_internal" [(set (match_operand:SI 0 "register_operand" "=a") (xor:SI (match_operand:SI 1 "register_operand" "%r") (match_operand:SI 2 "register_operand" "r")))] |