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| author | Max Filippov <jcmvbkbc@gmail.com> | 2020-04-13 13:26:04 -0700 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2020-04-14 16:55:40 -0700 |
| commit | a288e202c5e50704968685fc2922d159335be2cb (patch) | |
| tree | 052fab83de36d97b4b78981d3280f6bbff50fce9 /gcc | |
| parent | ae046fa25e5d4a905cc7fab028d0f92cb21dc972 (diff) | |
| download | gcc-a288e202c5e50704968685fc2922d159335be2cb.zip gcc-a288e202c5e50704968685fc2922d159335be2cb.tar.gz gcc-a288e202c5e50704968685fc2922d159335be2cb.tar.bz2 | |
xtensa: fix PR target/94584
Patterns zero_extendhisi2, zero_extendqisi2 and extendhisi2_internal can
load value from memory, but they don't treat volatile memory correctly.
Add %v1 before load instructions to emit 'memw' instruction when
-mserialize-volatile is in effect.
2020-04-14 Max Filippov <jcmvbkbc@gmail.com>
gcc/
* config/xtensa/xtensa.md (zero_extendhisi2, zero_extendqisi2)
(extendhisi2_internal): Add %v1 before the load instructions.
gcc/testsuite/
* gcc.target/xtensa/pr94584.c: New test.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/xtensa/xtensa.md | 6 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/xtensa/pr94584.c | 24 |
4 files changed, 38 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e88c0e1..3c6a45e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2020-04-14 Max Filippov <jcmvbkbc@gmail.com> + + PR target/94584 + * config/xtensa/xtensa.md (zero_extendhisi2, zero_extendqisi2) + (extendhisi2_internal): Add %v1 before the load instructions. + 2020-04-14 Aaron Sawdey <acsawdey@linux.ibm.com> PR target/94542 diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md index 5b803d3..749fe47 100644 --- a/gcc/config/xtensa/xtensa.md +++ b/gcc/config/xtensa/xtensa.md @@ -538,7 +538,7 @@ "" "@ extui\t%0, %1, 0, 16 - l16ui\t%0, %1" + %v1l16ui\t%0, %1" [(set_attr "type" "arith,load") (set_attr "mode" "SI") (set_attr "length" "3,3")]) @@ -549,7 +549,7 @@ "" "@ extui\t%0, %1, 0, 8 - l8ui\t%0, %1" + %v1l8ui\t%0, %1" [(set_attr "type" "arith,load") (set_attr "mode" "SI") (set_attr "length" "3,3")]) @@ -575,7 +575,7 @@ "" "@ sext\t%0, %1, 15 - l16si\t%0, %1" + %v1l16si\t%0, %1" [(set_attr "type" "arith,load") (set_attr "mode" "SI") (set_attr "length" "3,3")]) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 3a3a1c5..69f9b93 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2020-04-13 Max Filippov <jcmvbkbc@gmail.com> + + PR target/94584 + * gcc.target/xtensa/pr94584.c: New test. + 2020-04-14 Iain Sandoe <iain@sandoe.co.uk> PR c++/94359 diff --git a/gcc/testsuite/gcc.target/xtensa/pr94584.c b/gcc/testsuite/gcc.target/xtensa/pr94584.c new file mode 100644 index 0000000..1577285 --- /dev/null +++ b/gcc/testsuite/gcc.target/xtensa/pr94584.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mserialize-volatile" } */ + +unsigned long load32 (volatile unsigned long *s) +{ + return *s; +} + +short load16s (volatile short *s) +{ + return *s; +} + +unsigned short load16u (volatile unsigned short *s) +{ + return *s; +} + +unsigned char load8 (volatile unsigned char *s) +{ + return *s; +} + +/* { dg-final { scan-assembler-times "memw" 4 } } */ |