RISC-V: Force scalable vector on all vsetvl tests

Since when VLEN = 128bits and FIXED-VLMAX, vsetvli a5,zero will be optimized into vsetivli zero, 16 for SEW = 16. Such situation will cause many bogus FAILs in FIXED-VLMAX of full coverage testing. Force them all scalable vectors to supress those bogus FAILs. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/vsetvl/avl_multiple-1.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_multiple-10.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_multiple-11.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_multiple-12.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_multiple-13.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_multiple-14.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_multiple-15.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_multiple-16.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_multiple-2.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_multiple-5.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_multiple-6.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_multiple-9.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_prop-1.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_prop-2.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-1.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-10.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-100.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-101.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-102.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-103.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-104.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-105.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-106.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-107.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-108.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-109.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-11.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-12.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-13.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-14.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-15.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-16.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-17.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-18.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-19.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-2.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-20.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-21.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-22.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-23.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-24.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-25.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-26.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-27.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-28.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-29.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-3.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-30.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-31.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-32.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-33.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-34.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-35.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-36.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-37.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-38.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-39.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-4.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-40.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-41.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-42.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-43.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-44.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-45.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-46.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-47.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-48.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-49.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-5.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-50.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-51.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-52.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-53.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-54.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-55.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-56.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-57.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-58.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-59.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-6.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-60.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-61.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-62.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-63.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-64.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-65.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-66.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-67.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-68.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-69.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-7.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-70.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-71.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-72.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-73.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-74.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-75.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-76.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-77.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-78.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-79.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-8.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-80.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-81.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-82.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-83.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-84.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-85.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-86.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-87.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-88.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-89.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-9.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-90.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-91.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-92.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-93.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-94.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-95.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-96.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-97.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-98.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/avl_single-99.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/dump-1.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/ffload-1.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/ffload-2.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/ffload-3.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/ffload-5.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/ffload-6.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/ffload-7.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-1.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-10.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-11.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-12.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-13.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-2.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-5.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-6.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-7.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-8.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-9.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/imm_conflict-1.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/imm_conflict-2.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/imm_conflict-3.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-11.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-12.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-13.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-14.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-15.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-16.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-17.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-4.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-7.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-8.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-9.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/imm_switch-1.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/imm_switch-2.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/imm_switch-3.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/imm_switch-4.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/imm_switch-5.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/imm_switch-6.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/imm_switch-7.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/imm_switch-8.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/imm_switch-9.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/pr108270.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/pr109399.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/pr109547.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/pr109615.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/pr109743-1.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/pr109743-2.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/pr109743-3.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/pr109743-4.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/pr109748.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/pr109773-1.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/pr109773-2.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/pr109974.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/pr111037-1.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/pr111037-2.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/pr111037-3.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/pr111037-4.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/pr111234.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/pr111255.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/pr111927.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/pr111947.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/pr112092-1.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/pr112092-2.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/pr112713-1.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/pr112713-2.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/pr112776.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/pr112813-1.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/pr112929-1.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/pr112988-1.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-11.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-12.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-34.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-36.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-38.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-39.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-4.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-40.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-41.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-42.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-43.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-44.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-46.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-5.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-6.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-1.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-13.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-14.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-15.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-16.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-2.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-21.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-22.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-23.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-24.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-4.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-5.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-6.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-7.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-8.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_call-1.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_call-2.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_call-3.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_call-4.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-1.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-2.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-10.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-13.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-6.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-9.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-1.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-10.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-11.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-12.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-13.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-14.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-15.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-16.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-2.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-3.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-4.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-5.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-6.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-7.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-8.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-9.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-6.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-7.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-8.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-1.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-13.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-3.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vsetvl-1.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vsetvl-10.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vsetvl-11.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vsetvl-12.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vsetvl-13.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vsetvl-14.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vsetvl-15.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vsetvl-16.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vsetvl-17.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vsetvl-18.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vsetvl-19.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vsetvl-2.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vsetvl-20.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vsetvl-21.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vsetvl-22.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vsetvl-23.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vsetvl-24.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vsetvl-3.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vsetvl-4.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vsetvl-5.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vsetvl-6.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vsetvl-7.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vsetvl-8.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vsetvl-9.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vsetvl_bug-1.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vsetvl_int.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-1.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-10.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-11.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-12.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-13.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-14.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-16.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-17.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-18.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-19.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-20.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-7.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-8.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-9.c: Force scalable vector. * gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c: Force scalable vector.
author: Juzhe-Zhong <juzhe.zhong@rivai.ai> 2023-12-19 16:42:30 +0800
committer: Pan Li <pan2.li@intel.com> 2023-12-19 16:45:55 +0800
commit: a0cc5eb21de80136ddb104cfb3c6994b5de87bbe (patch)
tree: 279c89b11c1b3939f43a24913cb5de4dc98cdb5b /gcc
parent: 746e7b214d61879c3531c0f0fe34656764a26906 (diff)
download: gcc-a0cc5eb21de80136ddb104cfb3c6994b5de87bbe.zip
gcc-a0cc5eb21de80136ddb104cfb3c6994b5de87bbe.tar.gz
gcc-a0cc5eb21de80136ddb104cfb3c6994b5de87bbe.tar.bz2
446 files changed, 451 insertions, 451 deletions
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-1.c
index 7bad3fb..70eb5d7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-10.c
index 77adaa7..d98d965 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-11.c
index 06cae83..799e29b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-12.c
index c94c387..36de289 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-12.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-13.c
index 41674f4..00e1931 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-13.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-14.c
index 10be734..4c43ae0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-14.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-15.c
index 2e2eb3e..a5b576a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-15.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-16.c
index 777d909..48abfd1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-16.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-2.c
index 0f0370d..844d1fc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c
index 43f272f..da69a5b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c
index c1f3cfc..1d1bf10 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-5.c
index 374b7af..a3ffc3c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-6.c
index efd1e4e..ea91076 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c
index 96dc76f..e605331 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c
index 9ada32e..024087a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-9.c
index 803c696..85a59f8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-1.c
index 19ea0f1..6e07988 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-2.c
index fdef8e3..567e50a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O3 --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gc_zve32f -mabi=lp64d -O3 --param=riscv-autovec-preference=fixed-vlmax" } */
 
 int d0, sj, v0, rp, zi;
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-1.c
index 83f7f1d..4ef4c51 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-10.c
index 01fc236..248e80a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-100.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-100.c
index d2c5a4b..04bb681 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-100.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-100.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-101.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-101.c
index 4be7d83..ba341c7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-101.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-101.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-102.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-102.c
index ae1208c..739c550 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-102.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-102.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-103.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-103.c
index 51306fd..c9c4c92 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-103.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-103.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-104.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-104.c
index fb3577d..9c2fa0a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-104.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-104.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-105.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-105.c
index 708a3bd..3f0a6be 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-105.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-105.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-106.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-106.c
index e63d52d..b21adc0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-106.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-106.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c
index e424b4b..dce918e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-108.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-108.c
index 95f1a95..325bc59 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-108.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-108.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-109.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-109.c
index a45e52b..f99126c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-109.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-109.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-11.c
index 3cb776e..37ac5da 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-12.c
index 027bc38..ca5ffad 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-12.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-13.c
index 984d559..33e9572 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-13.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-14.c
index e464ceb..2c9a896 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-14.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-15.c
index e32b60f..135cdbf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-15.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-16.c
index d15499b..7b8ec62 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-16.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-17.c
index ad2b340..5e0906f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-17.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-18.c
index 3860c6d..b73ef38 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-18.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-19.c
index 350e1d0..a2ba509 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-19.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-2.c
index 4108dd3..721ae13 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-20.c
index cda2e0e..8af7265 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-20.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-20.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-21.c
index d949933..d461781 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-21.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-21.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-22.c
index d5e5f5a..9939834 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-22.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-22.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-23.c
index ec59d58..6f8e714 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-23.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-24.c
index 2fd0964..a2d0eca 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-24.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-24.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-25.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-25.c
index cfb7d78..c19958c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-25.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-25.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-26.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-26.c
index a7e067e..769673a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-26.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-26.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-27.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-27.c
index 0fa72c3..1d422e9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-27.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-27.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-28.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-28.c
index d5f9091..386fb5b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-28.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-28.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-29.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-29.c
index 44297d1..652d3eb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-29.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-29.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-3.c
index 136dcb4..754f426 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-30.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-30.c
index 92df178..305caf3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-30.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-30.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-31.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-31.c
index 9afa547..3defd39 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-31.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-31.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-32.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-32.c
index 31363d2..370171b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-32.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-33.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-33.c
index f4f58cd..43ee066 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-33.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-33.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-34.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-34.c
index d28c12b..6d63a8b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-34.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-34.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-35.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-35.c
index d1daafd..8fdadff 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-35.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-35.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-36.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-36.c
index 7db2dc5..1db27d8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-36.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-36.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-37.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-37.c
index 0c6a251..092e2aa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-37.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-37.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-38.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-38.c
index 8606b10..9f5896b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-38.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-38.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-39.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-39.c
index 20e0e4d..d278db5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-39.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-39.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-4.c
index 51c1f83..1f4d784 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-40.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-40.c
index 796b40f..926dc63 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-40.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-40.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-41.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-41.c
index 5b79594..4dedf36 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-41.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-41.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-42.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-42.c
index 5e66bc4..86c51f9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-42.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-42.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-43.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-43.c
index 1523d4b..8f22056 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-43.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-43.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-44.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-44.c
index 443758d..5b7582b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-44.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-44.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-45.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-45.c
index 0ff8226..8b02f99 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-45.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-45.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-46.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-46.c
index a60674d..0f0feec 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-46.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-46.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-47.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-47.c
index 1140320..5c451d3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-47.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-47.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-48.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-48.c
index f145348..921a6d2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-48.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-48.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-49.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-49.c
index 77fe05b..67f3d45 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-49.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-49.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-5.c
index aa3b937..9aa0c99 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-50.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-50.c
index e7bdb6d..786d5d6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-50.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-50.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-51.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-51.c
index 2451e7c..3f4ee86 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-51.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-51.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-52.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-52.c
index 882576e..69c89a7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-52.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-52.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-53.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-53.c
index dbdb025..645cf06 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-53.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-53.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-54.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-54.c
index 7b85cc7..c8bba03 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-54.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-54.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-55.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-55.c
index 6c7aeea..e9fbc73 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-55.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-55.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-56.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-56.c
index 5d0584e..f5a02fe 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-56.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-56.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-57.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-57.c
index a41065b..2eb6e43 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-57.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-57.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-58.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-58.c
index 610b731..6f57200 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-58.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-58.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-59.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-59.c
index 82b82ae..9ea60a1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-59.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-59.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-6.c
index 1ed0355..a928e46 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-60.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-60.c
index 731184d..d156c39 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-60.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-60.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-61.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-61.c
index 5e7dabf..5bffa37 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-61.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-61.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-62.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-62.c
index fbc4d58..e196906 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-62.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-62.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-63.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-63.c
index 5433b18..0e62ad3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-63.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-63.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-64.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-64.c
index 093f67f..290e941 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-64.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-65.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-65.c
index 1ccd234..775f72f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-65.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-65.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-66.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-66.c
index aac6b52..9cc630c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-66.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-66.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.c
index 7e77e0e..2a2c35a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c
index a366a15..632d464 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-69.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-69.c
index 633c4af..369961f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-69.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-69.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-7.c
index bd407b2..8e82034 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-70.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-70.c
index 8927fb1..acd96f6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-70.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-70.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c
index c59cc00..e945882 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c
index 45b00f6..0c00da4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-73.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-73.c
index 53d4500..7360c87 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-73.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-73.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-74.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-74.c
index cc4f88b..fb7d874 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-74.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-74.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-75.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-75.c
index c85f186..9198a62 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-75.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-75.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-76.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-76.c
index 142e43c..d7975b9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-76.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-76.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-77.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-77.c
index ddd6766..a638d21 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-77.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-77.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-78.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-78.c
index 7df8f24..5d9778d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-78.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-78.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-79.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-79.c
index 344909a..5bb00de 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-79.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-79.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-8.c
index 1eb7546..718abcf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-80.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-80.c
index 0200d72..5ea4757 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-80.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-80.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-81.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-81.c
index fe67357..be0787d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-81.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-81.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-82.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-82.c
index 17bac422..0cdd656 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-82.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-82.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-83.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-83.c
index c7a3383..dd39a65 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-83.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-83.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-84.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-84.c
index 5cd0f28..91c899c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-84.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-84.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-85.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-85.c
index f071fa2..b513beb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-85.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-85.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-86.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-86.c
index 48636f5..9a4217f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-86.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-86.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-87.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-87.c
index 5463cd8..0b22c04 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-87.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-87.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-88.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-88.c
index 5b64cfe..ff0f746 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-88.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-88.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-89.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-89.c
index 65bff4d..bdd74d6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-89.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-89.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-9.c
index 8f47258..a81ed65 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-90.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-90.c
index 92fee67..1c98ec5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-90.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-90.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-91.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-91.c
index 3eadab3..c39fea4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-91.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-91.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.c
index ae60519..1ff85ad 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-93.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-93.c
index eaed7f1..1701f6b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-93.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-93.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-94.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-94.c
index a2f32df..d36d69f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-94.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-94.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-95.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-95.c
index 128a629..a075688 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-95.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-95.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-96.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-96.c
index 19516eb..abe54e8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-96.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-96.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-97.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-97.c
index 46437a1..6e62419 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-97.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-97.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-98.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-98.c
index 96e3371..7aab0e0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-98.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-98.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-99.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-99.c
index 423dba7..7a06d70 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-99.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-99.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/dump-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/dump-1.c
index fb4edb4..5b4bd43 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/dump-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/dump-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fdump-rtl-vsetvl-details" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fdump-rtl-vsetvl-details" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-1.c
index b2b7eaf..5e87191 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-2.c
index c0e21d4..211a1c5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-3.c
index 9e90b18..6113e36 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-5.c
index 04eb78b..d893492 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-6.c
index 1b32f4a..78c785a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-7.c
index 1c08b75..0cf6c4f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-1.c
index 691980f..19044ea 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-10.c
index cdb2c8f..e540e96 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-11.c
index ba2d57e..7afac64 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-12.c
index ced6cb8..9097f72 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-12.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-13.c
index fd75172..28c6d35 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-13.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-2.c
index 3fa7cf3..ac65a12 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c
index a689474..e9273f0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c
index 13d7c23..d22aef6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-5.c
index 21be9c0..3189929 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-6.c
index 92d830c..381589e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-7.c
index 550c3a3..b3d2907 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-8.c
index 667effa..9ca53ab 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-9.c
index 94d08bc..82872f1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-1.c
index 331ebab..22645c0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-2.c
index 3ed73ea..55419d2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-3.c
index 2fa29c0..a82f76b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c
index 0262ff1..48ba536 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c
index 9b5917e..611c35a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c
@@ -1,7 +1,7 @@
 #include "riscv_vector.h"
 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.c
index 618adb7..e198892 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.c
index c9d4950..a045681 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-11.c
index 2e8647e..79061f4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-12.c
index bca7089..3945dca 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-12.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-13.c
index 21cd029..7266c59 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-13.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-14.c
index 834328d..9a02380 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-14.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-15.c
index e535f8d..cceabd7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-15.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-16.c
index b4dee19..185f971 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-16.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-17.c
index a8c19a2..48ec42d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-17.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.c
index 32f3394..8a601c1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.c
index 4d08475..80dfbff 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-4.c
index 976d389..e2bac85 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.c
index defeb86..784ff3c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.c
index 1ae8a03..ade612b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-7.c
index ac943abe..7ae5c5a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-8.c
index 731930e..1b7ce74 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-9.c
index 2dfca07..b6c5bcd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-1.c
index b084eea..bcdbe75 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-2.c
index c55faa5..6477daf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-3.c
index a751700..79d2eb8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-move-loop-invariants" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-move-loop-invariants" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-4.c
index b8aac96..642a089 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-5.c
index 7adf9aa..a476994 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-6.c
index e4f379d..5fa6c8b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-7.c
index af110ec..e8a1fd0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-8.c
index f8568a8..c92e59e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-9.c
index 322e271..19bee67 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr108270.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr108270.c
index d2ae43b..4fab8e4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr108270.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr108270.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109399.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109399.c
index b3abad7..1daba8f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109399.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109399.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109547.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109547.c
index 88dd877..0ddb261 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109547.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109547.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109615.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109615.c
index 90b0bb7..33a073a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109615.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109615.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-1.c
index e927829..273eb43 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-2.c
index e87dc03..7fe7be6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-3.c
index 98630a1..3f06b6e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-4.c
index edd1285..87ec80e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109748.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109748.c
index 81c42c5..9bb1302 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109748.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109748.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-1.c
index 7a9882b..7848ff2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-2.c
index 7bfbaaf..80e9abc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c
index 06a8562..0efd15b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv_zbb -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv_zbb -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -O3" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-1.c
index 0b7b32f..64ca51b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-2.c
index ac50da7..71d2c9a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64d_zvfh -mabi=ilp32d -O3" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gc_zve64d_zvfh -mabi=ilp32d -O3" } */
 
 #include "pr111037-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c
index 13344ec..110e55b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.c
index 1a0fcf7..76dd7cb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c
index ee5eec4..d8f2cbd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3" } */
 
 #include <riscv_vector.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111255.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111255.c
index d667dbc..a19d920 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111255.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111255.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param riscv-autovec-lmul=m2 -fno-vect-cost-model" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3 --param riscv-autovec-lmul=m2 -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111927.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111927.c
index ab599ad..61dcc53 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111927.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111927.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111947.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111947.c
index cea19b7..14192be 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111947.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111947.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O2 -Wno-implicit-int" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O2 -Wno-implicit-int" } */
 
 char *a;
 b() {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112092-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112092-1.c
index 857ab0c..7722751 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112092-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112092-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112092-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112092-2.c
index 2b0844f..727b2db 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112092-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112092-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-1.c
index 76402ab..06e4b2d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-2.c
index 04539d9..2cae1b4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112776.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112776.c
index 8536901..b60853d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112776.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112776.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112813-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112813-1.c
index 5aab9c2..c0a6bf2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112813-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112813-1.c
@@ -1,6 +1,6 @@
 /* Test that we do not have ice when compile */
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -O3" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv_zvl256b -mabi=ilp32d -O3" } */
 
 int a, c, d, f, j;
 int b[7];
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112929-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112929-1.c
index 0435e5d..c3ecbf8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112929-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112929-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3" } */
 
 int printf(char *, ...);
 int a, l, i, p, q, t, n, o;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112988-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112988-1.c
index b37166b..27f0b18 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112988-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112988-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3" } */
 
 int a = 0;
 int p, q, r, x = 230;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c
index b0c40e8..bb01691 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c
index d1713ba..3b42566 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-11.c
index 627debf..e8551ec 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-12.c
index 192f1f3..50d8d0d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-12.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.c
index 50c4fbd..44a0700 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c
index efb45ff..e702c5e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c
index d0d9ec9..9d037f6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c
index b0e23b9..899df3e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c
index 52f61b2..f19897a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c
index 82d06f9..3a033bb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c
index 604597d..2b9fbd2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.c
index a09f504..b5a02c0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c
index 52f61b2..f19897a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c
index 9018deb..9c0c319 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c
index 6b773e0..e293d86 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c
index 91e75b0..f227e5c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.c
index fe41d15..df6e16e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c
index d0fdc5f..71a608f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c
index d0e7525..8373067 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c
index f239114..fb12365 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c
index 464457c..4583504 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c
index 2a20b32..f16f4b9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c
index a16c5f5..93ec13a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c
index 227ceed..9b0d88d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c
index 0632eac..ee321fc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c
index dfae531..43b443b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c
index aa01648..6785558 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-34.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-34.c
index 6feecdf..8c4c47e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-34.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-34.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.c
index e0b5fbb..99dbbba 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-36.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-36.c
index 9be774c..40bff0f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-36.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-36.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c
index 3625f04..857dc3a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-38.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-38.c
index cae22dd..b067f9b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-38.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-38.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-39.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-39.c
index 9fca90c..eeacb8e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-39.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-39.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-4.c
index fd2ba44..75ef23f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-40.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-40.c
index c3acdea..b639251 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-40.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-40.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-41.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-41.c
index d8a6aa2..bea7ede 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-41.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-41.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-42.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-42.c
index 739d4bc..5a361b5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-42.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-42.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-43.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-43.c
index f8e2c4d..f0e0ff6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-43.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-43.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-44.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-44.c
index e5239be..5e562fa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-44.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-44.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.c
index 2721ebb..9dc954a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-46.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-46.c
index ca64d49..fddaeae 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-46.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-46.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-5.c
index b38e362..b353b06 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-6.c
index e98596f..80a8046 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.c
index b508abd..d9965ca 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.c
index dd4797b..0e84394 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.c
index 4f31d14..95a227b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-1.c
index 20c2193..d6b6a2b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c
index db8c23f..9e01bffd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c
index 025a6de..f9f2420 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c
index c18aa3c..ecacd4b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-13.c
index 76e3605..fd4f6d5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-13.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-14.c
index 3e5e887..4436cd9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-14.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-15.c
index b66df6a..16b2c32 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-15.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-16.c
index 1b33c17..12bb03d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-16.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c
index 5b2b2e1..0eadad1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c
index 618e812..8679fab 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c
index 6bdb2e9..9130d1c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-2.c
index e61eb40..18e41b9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c
index db4f9a1..394553d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-21.c
index 26f115c..048087f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-21.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-21.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-22.c
index 6fb81c51..1a4fdb1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-22.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-22.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-23.c
index 728761d..9247589 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-23.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-24.c
index 8dbcccd..9e811a9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-24.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-24.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.c
index 1dee56d..738b53f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.c
index 8547d4a..0cbc6a4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.c
index 5240fe3..e7846f0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.c
index f0e1ada..9b2b0ae 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c
index 830e910..c0735a5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-4.c
index 81cdad2..cb90750 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-5.c
index de84f9e..a63eae7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-6.c
index 9054d86..607c802 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-7.c
index 8265b5e..48f3cdf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-8.c
index 5161530..610c944 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c
index 8dbc41b..7ea1218 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-1.c
index 3441b1f..1dae707 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-2.c
index da56097..1e72f61 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-3.c
index 748f54e..62d087d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-4.c
index 164c44a..e52a55e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-1.c
index 6ca0d17..0341845 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-2.c
index 2c436d8..85686e8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c
index bb75c50..0b03e75 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-10.c
index 30de699..d72414f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.c
index 653aba8..2a55f2d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.c
index 00a7594..eb2a710 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-13.c
index d367690..7a4b0a7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-13.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c
index 72f49f3..0dbda08 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c
index 88a565f..66e1b73 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c
index b0ca394..28ffe2c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c
index efba512..5a3e05e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-6.c
index 01396ef..bb2ca39 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c
index dd0d51d..293b109 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.c
index fbca9b0..ddc293b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-9.c
index bc52e5a..87ea397 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c
index 429d494..d296fe6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c
index 2fe6605..510e0de 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c
index 3c45894..f5a9f6a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c
index 2f2f089..73eb9c7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c
index 8774155..c925bcf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c
index 8004854..94325b4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.c
index 9e8f801..9de3aa3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.c
index 204fe95..9ed3bfd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.c
index 0868c01..ef3f76a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.c
index 44e170b..302b2f6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.c
index 80bd008..1dd7933 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c
index 9cdaa06..756036e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.c
index 5517180..a5d6c9a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.c
index 2619047..ffbe7c8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.c
index d5e8728..0c5a119 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.c
index 19bfd58..b1faaee 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.c
index 2f13d2c..b80bdde 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.c
index 32a8edb..c0b8b4c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.c
index 897c1ab..5366b8b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.c
index 2ba5e28..3a3e9bc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.c
index d56d264..181d0e7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c
index f318342..8c67890 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c
index 4cf5a00..597e066 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c
index f708e4a..02a08cc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c
index f3dbffb..b6cf5ab 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c
index 6e26896..c7fec26 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c
index 6dde53e..a89c1d5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c
index 903c46c..f39b32c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c
index 830dfb8..6f61bb6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c
index 898dd20..b42c2b2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c
index 24a3f55..8caeed7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c
index f311cbf..d129caf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c
index 2e0fbc5..830739d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c
index 7a0e12f..e4ff921 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c
index f612607..f8e6ed5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c
index 4dcbf7b..225749f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c
index 0e0b67c..1f27a6b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c
index 5a5b7d5..e91a4e4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c
index 9e1f9c7..d0a920f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c
index 5ac8e17..27e7892 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c
index 5ac73a9..8d37f7b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c
index f79559c..a3817a3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c
index a423c5d..369850a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c
index 00d2f82..a8c404d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c
index 69f21e5..ef691dd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c
index 65709cd..1345fa0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c
index 4bf3725..d6cbb2b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c
index cacd290..364bd69 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c
index 39e747b..5b26167 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c
index dedadcb..4cbfc67 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c
index 31be966..7a28e84 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c
index 5a48b99..8ca376e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c
index 8ea5349..4291d8d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c
index f4fa269..3e6599d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c
index 8526ae6..e767b12 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c
index 42180a7..0d5183e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-1.c
index fb1258f..e452d85 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 /* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-10.c
index bdfb964..7503fbe 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-11.c
index 17055f0..6b3439a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-12.c
index 1383995..3a739e2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-12.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-13.c
index ba4b5ef..ac0204f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-13.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-14.c
index 5f04c19..4a903cf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-14.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-15.c
index 8debc17..9fb73cf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-15.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-16.c
index c8913d8..e44537e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-16.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c
index d5f27c6..960c9bf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c
index c676b6b..5f22e8d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c
index 11f1da3..e5f35c0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-2.c
index 5ee37e9..b2f967b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 /* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-3.c
index ed38627..31ebc13 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 /* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-4.c
index d8f1a0b..bac607b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 /* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-5.c
index 293c818..a620523 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 /* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-6.c
index b047370..9c293dd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 /* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-7.c
index 04d1930..355a030 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 /* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-8.c
index abfbc1b..85668d0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 /* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-9.c
index 6528c11..71a0ccc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.c
index 15b10e6..f6ecebe 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -O3" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.c
index 823e50a..39576c1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.c
index 1dac01c..f5fb770 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.c
index 05321bf..63282f4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.c
index 016ad75..d9cdb11 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-6.c
index f96b8c5..1400e67 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-7.c
index c20e7b8..4824b75 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-8.c
index ca6b7fe..b798852 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-1.c
index 7648b8a..d314122 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c
index 204058a..0532c7d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c
index 99cf3bd..b664c4b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c
index b797585..04c4b88 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-13.c
index 29b8508..e2deea7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-13.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c
index 1fc97f8..0671bce 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c
index f3b3766..1bac9fd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c
index a1587e7..8dddd88 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c
index 9d40a13..c6b39aa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-3.c
index 00b883f..8ba5680 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c
index ce30f3a..1404c9d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c
index ce30f3a..1404c9d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c
index f7e3543..609c68d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c
index 28c017d..043f177 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c
index 06bb695..0bedde8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c
index 06bb695..0bedde8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c
index 0e76f67..c3519ce 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -Wno-psabi" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -Wno-psabi" } */
 
 #include "riscv_vector.h"
 
@@ -13,4 +13,4 @@ void f(int8_t *base, int8_t *out, size_t vl, size_t m, vbool64_t mask) {
 }
 
 /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
-\ No newline at end of file
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-10.c
index 3c7e0ec..9a55309 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-11.c
index b665bb8..81bb251 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-12.c
index fc7e1cb..6fe2813 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-12.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-13.c
index 1ea248d..765ac30 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-13.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-14.c
index 40d4af00..992c2a1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-14.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-15.c
index a1954e7..d218d04 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-15.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-16.c
index 29e05c4..d06203a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-16.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-17.c
index 8a1bbb4..fb05c11 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-17.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-18.c
index 5799220..ee1501e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-18.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-19.c
index 87ef3ac..1544f02 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-19.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-2.c
index ff0171b..810f9f3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-20.c
index d3f4a27..854568f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-20.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-20.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-21.c
index 551920c..c134f55 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-21.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-21.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-22.c
index 98df431..f519cd4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-22.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-22.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c
index e3d069f..e2b84d6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c
index 1703c73..493ef97 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d" } */
 
 #include <riscv_vector.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-3.c
index 13d09fc..a7539b5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-4.c
index 4163931..bfa798f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-5.c
index e84e32b..6e1e44f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-6.c
index fb7abde..4e6cc90 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-7.c
index 5fa2f2b..762558f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-8.c
index 55cc770..0b659fd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-9.c
index d07152c..ef7d022 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-1.c
index 45727a0..2cd966e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64 --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax -O2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv_zvl256b -mabi=lp64 --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax -O2" } */
 
 struct a_struct
 {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c
index bbc02ea..1b9f4d8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d --param=riscv-autovec-lmul=m4 -O3 -fomit-frame-pointer -funroll-loops" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv_zvl256b -mabi=lp64d --param=riscv-autovec-lmul=m4 -O3 -fomit-frame-pointer -funroll-loops" } */
 
 int safe_lshift_func_int32_t_s_s_left, safe_lshift_func_int32_t_s_s_right,
     safe_sub_func_uint64_t_u_u_ui2, safe_mul_func_uint64_t_u_u_ui2, g_79_2,
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_int.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_int.c
index 4cdd587..f340364 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_int.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_int.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-1.c
index 96f1690..bec3928 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-10.c
index 1204f83..be50905 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-11.c
index 637b0a5..3cf6b16 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-12.c
index e32994e..b9b6f26 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-12.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-13.c
index 0160d73..65a8415 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-13.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-14.c
index ae1db0a..08fd74f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-14.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
@@ -15,4 +15,4 @@ void f(int8_t *base, int8_t *out, size_t vl, size_t m) {
 
 /* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
-\ No newline at end of file
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c
index a849721..0143aa1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-16.c
index 6cce6fe..fe44fb3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-16.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
@@ -11,4 +11,4 @@ void foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out, size_t n, int c
   __riscv_vse32_v_i32m1(out, c, __riscv_vsetvlmax_e8mf2 ());
 }
 
-/* { dg-final { scan-assembler-times {vsetvli} 7 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
-\ No newline at end of file
+/* { dg-final { scan-assembler-times {vsetvli} 7 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-17.c
index d28d6f8..7d1f2e1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-17.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
@@ -13,4 +13,4 @@ void foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out, size_t n, int c
   }
 }
 
-/* { dg-final { scan-assembler-times {vsetvli} 7 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
-\ No newline at end of file
+/* { dg-final { scan-assembler-times {vsetvli} 7 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-18.c
index 8baedb0..de4ba0a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-18.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-19.c
index 1d77efb..91c2a4f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-19.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c
index 853ffee..975ba97 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-20.c
index 1102d7e..bfe575e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-20.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-20.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
@@ -16,4 +16,4 @@ void foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out, size_t n, int c
   }
 }
 
-/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */
-\ No newline at end of file
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.c
index cc0135f..466f3a8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c
index 2a535b5..5acc2ac 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.c
index 0e6b14e..b2e3382 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.c
index c32f15d..558690a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-7.c
index 15e9953..a679f54 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-8.c
index caa2103..d350752 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-9.c
index 1204f83..be50905 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c
index 5d11267..d36560b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv_zvl256b -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -O3" } */
 
 
 #include <stdint-gcc.h>
author	Juzhe-Zhong <juzhe.zhong@rivai.ai>	2023-12-19 16:42:30 +0800
committer	Pan Li <pan2.li@intel.com>	2023-12-19 16:45:55 +0800
commit	a0cc5eb21de80136ddb104cfb3c6994b5de87bbe (patch)
tree	279c89b11c1b3939f43a24913cb5de4dc98cdb5b /gcc
parent	746e7b214d61879c3531c0f0fe34656764a26906 (diff)
download	gcc-a0cc5eb21de80136ddb104cfb3c6994b5de87bbe.zip gcc-a0cc5eb21de80136ddb104cfb3c6994b5de87bbe.tar.gz gcc-a0cc5eb21de80136ddb104cfb3c6994b5de87bbe.tar.bz2