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| author | Jakub Jelinek <jakub@redhat.com> | 2020-01-09 09:20:25 +0100 |
|---|---|---|
| committer | Jakub Jelinek <jakub@gcc.gnu.org> | 2020-01-09 09:20:25 +0100 |
| commit | a0ab54de0ec3e0d48b2a681f7f78fe14bc4099eb (patch) | |
| tree | 8037e4dcbc3ba93e09417edb92f5cf502fdc4a36 /gcc | |
| parent | ec9b602c167fb7dfba717f04852a3810ecf9a9a8 (diff) | |
| download | gcc-a0ab54de0ec3e0d48b2a681f7f78fe14bc4099eb.zip gcc-a0ab54de0ec3e0d48b2a681f7f78fe14bc4099eb.tar.gz gcc-a0ab54de0ec3e0d48b2a681f7f78fe14bc4099eb.tar.bz2 | |
re PR inline-asm/93202 ([RISCV] ICE when using inline asm 'h' operand modifier)
PR inline-asm/93202
* config/riscv/riscv.c (riscv_print_operand_reloc): Use
output_operand_lossage instead of gcc_unreachable.
* doc/md.texi (riscv f constraint): Fix typo.
* gcc.target/riscv/pr93202.c: New test.
From-SVN: r280030
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/riscv/riscv.c | 3 | ||||
| -rw-r--r-- | gcc/doc/md.texi | 2 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 3 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/pr93202.c | 10 |
5 files changed, 21 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 2756a97..1fda5d1 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2020-01-09 Jakub Jelinek <jakub@redhat.com> + PR inline-asm/93202 + * config/riscv/riscv.c (riscv_print_operand_reloc): Use + output_operand_lossage instead of gcc_unreachable. + * doc/md.texi (riscv f constraint): Fix typo. + PR target/93141 * config/i386/i386.md (subv<mode>4): Use SWIDWI iterator instead of SWI. Use <general_hilo_operand> instead of <general_operand>. Use diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c index 4ba8111..320a70b 100644 --- a/gcc/config/riscv/riscv.c +++ b/gcc/config/riscv/riscv.c @@ -3191,7 +3191,8 @@ riscv_print_operand_reloc (FILE *file, rtx op, bool hi_reloc) break; default: - gcc_unreachable (); + output_operand_lossage ("invalid use of '%%%c'", hi_reloc ? 'h' : 'R'); + return; } fprintf (file, "%s(", reloc); diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index cc4a292..cec74ea 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -3518,7 +3518,7 @@ The @code{X} register. @table @code @item f -A floating-point register (if availiable). +A floating-point register (if available). @item I An I-type 12-bit signed immediate. diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 53766af..b4e4f83 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,8 @@ 2020-01-09 Jakub Jelinek <jakub@redhat.com> + PR inline-asm/93202 + * gcc.target/riscv/pr93202.c: New test. + PR target/93141 * gcc.target/i386/pr93141-1.c: Add tests with constants that have MSB of the low half of the constant set. diff --git a/gcc/testsuite/gcc.target/riscv/pr93202.c b/gcc/testsuite/gcc.target/riscv/pr93202.c new file mode 100644 index 0000000..d8091b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr93202.c @@ -0,0 +1,10 @@ +/* PR inline-asm/93202 */ +/* { dg-do compile { target fpic } } */ +/* { dg-options "-fpic" } */ + +void +foo (void) +{ + asm volatile ("%h0" :: "i" (&foo)); /* { dg-error "invalid use of '%h'" } */ + asm volatile ("%R0" :: "i" (&foo)); /* { dg-error "invalid use of '%R'" } */ +} |