aboutsummaryrefslogtreecommitdiff
path: root/gcc
diff options
context:
space:
mode:
authorGCC Administrator <gccadmin@gcc.gnu.org>2021-10-14 00:16:31 +0000
committerGCC Administrator <gccadmin@gcc.gnu.org>2021-10-14 00:16:31 +0000
commit9eb28a0f19b290094a76889e90bd7fefa5da6d11 (patch)
tree9611f3df195371d892d0cf1197a6a0d1fe300320 /gcc
parentf874a13ca3870a56036a90758b0d41c8c217f4f7 (diff)
downloadgcc-9eb28a0f19b290094a76889e90bd7fefa5da6d11.zip
gcc-9eb28a0f19b290094a76889e90bd7fefa5da6d11.tar.gz
gcc-9eb28a0f19b290094a76889e90bd7fefa5da6d11.tar.bz2
Daily bump.
Diffstat (limited to 'gcc')
-rw-r--r--gcc/ChangeLog99
-rw-r--r--gcc/DATESTAMP2
-rw-r--r--gcc/fortran/ChangeLog6
-rw-r--r--gcc/testsuite/ChangeLog31
4 files changed, 137 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d7ca804..7eb01ec 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,102 @@
+2021-10-13 Roger Sayle <roger@nextmovesoftware.com>
+
+ * config/i386/i386-expand.c (ix86_expand_vector_move): Use a
+ pseudo intermediate when moving a SUBREG into a hard register,
+ by checking ix86_hardreg_mov_ok.
+ (ix86_expand_vector_extract): Store zero-extended SImode
+ intermediate in a pseudo, then set target using a SUBREG_PROMOTED
+ annotated subreg.
+ * config/i386/sse.md (mov<VMOVE>_internal): Prevent CSE creating
+ complex (SUBREG) sets of (vector) hard registers before reload, by
+ checking ix86_hardreg_mov_ok.
+
+2021-10-13 Indu Bhagat <indu.bhagat@oracle.com>
+
+ * ctfc.h (enum ctf_dtu_d_union_enum): Remove redundant comma.
+
+2021-10-13 Indu Bhagat <indu.bhagat@oracle.com>
+
+ * dwarf2ctf.c (gen_ctf_array_type): Fix typo in comment.
+
+2021-10-13 Martin Sebor <msebor@redhat.com>
+
+ PR middle-end/102630
+ * pointer-query.cc (compute_objsize_r): Handle named address spaces.
+
+2021-10-13 Iain Sandoe <iain@sandoe.co.uk>
+
+ * collect2.c (is_lto_object_file): Release simple-object
+ resources, close files.
+
+2021-10-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * config/arm/arm.c (thumb2_legitimate_address_p): Use VALID_MVE_MODE
+ when checking mve addressing modes.
+ (mve_vector_mem_operand): Fix the way we handle pre, post and offset
+ addressing modes.
+ (arm_print_operand): Fix printing of POST_ and PRE_MODIFY.
+ * config/arm/mve.md: Use mve_memory_operand predicate everywhere where
+ there is a single Ux constraint.
+
+2021-10-13 John David Anglin <danglin@gcc.gnu.org>
+
+ * config/pa/pa.md (muldi3): Add support for inlining 64-bit
+ multiplication on 32-bit PA 1.1 and 2.0 targets.
+
+2021-10-13 Martin Liska <mliska@suse.cz>
+
+ PR gcov-profile/90364
+ * coverage.c (build_info): Emit checksum to the global variable.
+ (build_info_type): Add new field for checksum.
+ (coverage_obj_finish): Pass object_checksum.
+ (coverage_init): Use 0 as checksum for .gcno files.
+ * gcov-dump.c (dump_gcov_file): Dump also new checksum field.
+ * gcov.c (read_graph_file): Read also checksum.
+ * doc/invoke.texi: Document the behaviour change.
+
+2021-10-13 Richard Biener <rguenther@suse.de>
+
+ * gimple-iterator.h (gsi_iterator_update): Add GSI_LAST_NEW_STMT,
+ start at integer value 2.
+ * gimple-iterator.c (gsi_insert_seq_nodes_before): Update
+ the iterator for GSI_LAST_NEW_STMT.
+ (gsi_insert_seq_nodes_after): Likewise.
+ * tree-if-conv.c (predicate_statements): Use GSI_LAST_NEW_STMT.
+ * tree-ssa.c (execute_update_addresses_taken): Correct bogus
+ arguments to gsi_replace.
+
+2021-10-13 Martin Liska <mliska@suse.cz>
+
+ PR target/102688
+ * common.opt: Use EnabledBy instead of detection in
+ finish_options and process_options.
+ * opts.c (finish_options): Remove handling of
+ x_flag_unroll_all_loops.
+ * toplev.c (process_options): Likewise for flag_web and
+ flag_rename_registers.
+
+2021-10-13 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/102659
+ * tree-if-conv.c (need_to_rewrite_undefined): New flag.
+ (if_convertible_gimple_assign_stmt_p): Mark the loop for
+ rewrite when stmts with undefined behavior on integer
+ overflow appear.
+ (combine_blocks): Predicate also when we need to rewrite stmts.
+ (predicate_statements): Rewrite affected stmts to something
+ with well-defined behavior on overflow.
+ (tree_if_conversion): Initialize need_to_rewrite_undefined.
+
+2021-10-13 Richard Biener <rguenther@suse.de>
+
+ PR ipa/102714
+ * ipa-sra.c (ptr_parm_has_nonarg_uses): Fix volatileness
+ check.
+
+2021-10-13 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * dwarf2ctf.c: Fix typo in comment.
+
2021-10-12 Bill Schmidt <wschmidt@linux.ibm.com>
PR target/101985
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index b902c81..4f146ee 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20211013
+20211014
diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index b97f189..f5d5d21 100644
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,9 @@
+2021-10-13 Tobias Burnus <tobias@codesourcery.com>
+
+ * dump-parse-tree.c (show_omp_clauses): Handle ancestor modifier,
+ avoid ICE for GFC_OMP_ATOMIC_SWAP.
+ * gfortran.h (gfc_omp_clauses): Change 'anecestor' into a bitfield.
+
2021-10-12 Tobias Burnus <tobias@codesourcery.com>
PR fortran/102541
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 0c70382..885e383 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,34 @@
+2021-10-13 Martin Sebor <msebor@redhat.com>
+
+ PR middle-end/102630
+ * gcc.target/i386/addr-space-2.c: Add -Wall.
+ * gcc.target/i386/addr-space-3.c: New test.
+
+2021-10-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * gcc.target/arm/mve/mve.exp: Make it test main directory.
+ * gcc.target/arm/mve/mve_load_memory_modes.c: New test.
+ * gcc.target/arm/mve/mve_store_memory_modes.c: New test.
+
+2021-10-13 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/102659
+ * gcc.dg/torture/pr69760.c: Adjust the testcase.
+ * gcc.target/i386/avx2-vect-mask-store-move1.c: Expect to move
+ the conversions to unsigned as well.
+
+2021-10-13 Richard Biener <rguenther@suse.de>
+
+ PR ipa/102714
+ * gcc.dg/ipa/pr102714.c: New testcase.
+
+2021-10-13 Kewen Lin <linkw@linux.ibm.com>
+
+ PR testsuite/102658
+ * gcc.target/powerpc/dform-1.c: Adjust as vectorization enabled at O2.
+ * gcc.target/powerpc/dform-2.c: Likewise.
+ * gcc.target/powerpc/pr80510-2.c: Likewise.
+
2021-10-12 Joseph Myers <joseph@codesourcery.com>
* gcc.dg/format/c11-printf-1.c, gcc.dg/format/c11-scanf-1.c,