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authorH.J. Lu <hjl.tools@gmail.com>2020-11-27 05:39:56 -0800
committerH.J. Lu <hjl.tools@gmail.com>2020-11-27 06:26:05 -0800
commit9df6c9c7a3936ff0a38a7066281842128cdd6914 (patch)
treec5cfa6e32ee9132ec93936b6a69479591812b704 /gcc
parent4b5726fda653d11f882fb9a112e4cffa12f7ed61 (diff)
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INSTALL: Default to --enable-cet=auto
PR other/98027 * doc/install.texi: Default to --enable-cet=auto.
Diffstat (limited to 'gcc')
-rw-r--r--gcc/doc/install.texi9
1 files changed, 4 insertions, 5 deletions
diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi
index 5f879ca..021c347 100644
--- a/gcc/doc/install.texi
+++ b/gcc/doc/install.texi
@@ -2259,11 +2259,10 @@ instrumentation, see @option{-fcf-protection} option. When
to add @option{-fcf-protection} and, if needed, other target
specific options to a set of building options.
-The option is disabled by default. When @code{--enable-cet=auto}
-is used, it is enabled on Linux/x86 if target binutils
-supports @code{Intel CET} instructions and disabled otherwise.
-In this case the target libraries are configured to get additional
-@option{-fcf-protection} option.
+@code{--enable-cet=auto} is default. CET is enabled on Linux/x86 if
+target binutils supports @code{Intel CET} instructions and disabled
+otherwise. In this case, the target libraries are configured to get
+additional @option{-fcf-protection} option.
@item --with-riscv-attribute=@samp{yes}, @samp{no} or @samp{default}
Generate RISC-V attribute by default, in order to record extra build