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| author | Christoph Müllner <christoph.muellner@vrull.eu> | 2023-03-27 12:51:51 +0200 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2023-03-27 14:18:47 +0200 |
| commit | 9da6f93144619b0f798c2b43d7cf4fc8d42c13a0 (patch) | |
| tree | 7f1dbad5e4b3f68c6f5e5a87a59cdd86783024ca /gcc | |
| parent | 3c0f5a9533bcb200d2d49755e653cf8f6c637118 (diff) | |
| download | gcc-9da6f93144619b0f798c2b43d7cf4fc8d42c13a0.zip gcc-9da6f93144619b0f798c2b43d7cf4fc8d42c13a0.tar.gz gcc-9da6f93144619b0f798c2b43d7cf4fc8d42c13a0.tar.bz2 | |
target/109296 - riscv: Add missing mode specifiers for XTheadMemPair
This patch adds missing mode specifiers for XTheadMemPair INSNs.
gcc/ChangeLog:
PR target/109296
* config/riscv/thead.md: Add missing mode specifiers.
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/riscv/thead.md | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md index 63c4af6..0623607 100644 --- a/gcc/config/riscv/thead.md +++ b/gcc/config/riscv/thead.md @@ -321,10 +321,10 @@ ;; MEMPAIR load DI extended signed SI (define_insn "*th_mempair_load_extendsidi2" - [(set (match_operand 0 "register_operand" "=r") - (sign_extend:DI (match_operand 1 "memory_operand" "m"))) - (set (match_operand 2 "register_operand" "=r") - (sign_extend:DI (match_operand 3 "memory_operand" "m")))] + [(set (match_operand:DI 0 "register_operand" "=r") + (sign_extend:DI (match_operand:SI 1 "memory_operand" "m"))) + (set (match_operand:DI 2 "register_operand" "=r") + (sign_extend:DI (match_operand:SI 3 "memory_operand" "m")))] "TARGET_XTHEADMEMPAIR && TARGET_64BIT && reload_completed && th_mempair_operands_p (operands, true, SImode)" { return th_mempair_output_move (operands, true, SImode, SIGN_EXTEND); } @@ -334,10 +334,10 @@ ;; MEMPAIR load DI extended unsigned SI (define_insn "*th_mempair_load_zero_extendsidi2" - [(set (match_operand 0 "register_operand" "=r") - (zero_extend:DI (match_operand 1 "memory_operand" "m"))) - (set (match_operand 2 "register_operand" "=r") - (zero_extend:DI (match_operand 3 "memory_operand" "m")))] + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI (match_operand:SI 1 "memory_operand" "m"))) + (set (match_operand:DI 2 "register_operand" "=r") + (zero_extend:DI (match_operand:SI 3 "memory_operand" "m")))] "TARGET_XTHEADMEMPAIR && TARGET_64BIT && reload_completed && th_mempair_operands_p (operands, true, SImode)" { return th_mempair_output_move (operands, true, SImode, ZERO_EXTEND); } |