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| author | Christophe Lyon <christophe.lyon@linaro.org> | 2016-05-18 12:46:23 +0000 |
|---|---|---|
| committer | Christophe Lyon <clyon@gcc.gnu.org> | 2016-05-18 14:46:23 +0200 |
| commit | 9d6e7c214fa58d5323d5c3cec87c86c894214180 (patch) | |
| tree | 6399aebed7168f7dc17216bf0e87a51f2d5e86a0 /gcc | |
| parent | b4dbe40e400e33b317ef83637477a5ec2b0a8c8b (diff) | |
| download | gcc-9d6e7c214fa58d5323d5c3cec87c86c894214180.zip gcc-9d6e7c214fa58d5323d5c3cec87c86c894214180.tar.gz gcc-9d6e7c214fa58d5323d5c3cec87c86c894214180.tar.bz2 | |
vreinterpret.c: Fix typo in comment.
* gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c: Fix typo in comment.
From-SVN: r236382
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c | 2 |
2 files changed, 6 insertions, 1 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index a0c3dc3..1ed9a5a 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,10 @@ 2016-05-18 Christophe Lyon <christophe.lyon@linaro.org> + * gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c: Fix typo + in comment. + +2016-05-18 Christophe Lyon <christophe.lyon@linaro.org> + * gcc.target/aarch64/noplt_3.c: Scan for "br\t". * gcc.target/aarch64/tail_indirect_call_1.c: Scan for "br\t", "blr\t" and switch to scan-assembler-times. diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c index 9e45e25..d4e5768 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c @@ -405,7 +405,7 @@ VECT_VAR_DECL(expected_q_f32_9,hfloat,32,4) [] = { 0xf3f2f1f0, 0xf7f6f5f4, VECT_VAR_DECL(expected_q_f32_10,hfloat,32,4) [] = { 0xfff1fff0, 0xfff3fff2, 0xfff5fff4, 0xfff7fff6 }; -/* Expected results for vreinterpretq_xx_f32. */ +/* Expected results for vreinterpret_xx_f32. */ VECT_VAR_DECL(expected_xx_f32_1,int,8,8) [] = { 0x0, 0x0, 0x80, 0xc1, 0x0, 0x0, 0x70, 0xc1 }; VECT_VAR_DECL(expected_xx_f32_2,int,16,4) [] = { 0x0, 0xc180, 0x0, 0xc170 }; |