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| author | liuhongt <hongtao.liu@intel.com> | 2021-09-10 10:15:58 +0800 |
|---|---|---|
| committer | liuhongt <hongtao.liu@intel.com> | 2021-09-28 11:00:29 +0800 |
| commit | 9cfb95f9b92326e86e99b50350ebf04fa9cd2477 (patch) | |
| tree | fabd1771c0d17d5f629c29d5d9a941a98979fa45 /gcc | |
| parent | 3540429be7ad1085af83600483908b621078fb6f (diff) | |
| download | gcc-9cfb95f9b92326e86e99b50350ebf04fa9cd2477.zip gcc-9cfb95f9b92326e86e99b50350ebf04fa9cd2477.tar.gz gcc-9cfb95f9b92326e86e99b50350ebf04fa9cd2477.tar.bz2 | |
Relax condition of (vec_concat:M(vec_select op0 idx0)(vec_select op0 idx1)) to allow different modes between op0 and M, but have same inner mode.
This will enable optimization for below pattern.
(set (reg:V2DF 87 [ xx ])
(vec_concat:V2DF (vec_select:DF (reg:V4DF 92)
(parallel [
(const_int 2 [0x2])
]))
(vec_select:DF (reg:V4DF 92)
(parallel [
(const_int 3 [0x3])
]))))
gcc/ChangeLog:
* simplify-rtx.c
(simplify_context::simplify_binary_operation_1): Relax
condition of simplifying (vec_concat:M (vec_select op0
index0)(vec_select op1 index1)) to allow different modes
between op0 and M, but have same inner mode.
gcc/testsuite/ChangeLog:
* gcc.target/i386/vect-rebuild.c: Adjust testcases.
* gcc.target/i386/avx512f-vect-rebuild.c: New test.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/simplify-rtx.c | 3 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/avx512f-vect-rebuild.c | 21 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/vect-rebuild.c | 2 |
3 files changed, 24 insertions, 2 deletions
diff --git a/gcc/simplify-rtx.c b/gcc/simplify-rtx.c index ebad5cb..16286be 100644 --- a/gcc/simplify-rtx.c +++ b/gcc/simplify-rtx.c @@ -4587,7 +4587,8 @@ simplify_context::simplify_binary_operation_1 (rtx_code code, if (GET_CODE (trueop0) == VEC_SELECT && GET_CODE (trueop1) == VEC_SELECT && rtx_equal_p (XEXP (trueop0, 0), XEXP (trueop1, 0)) - && GET_MODE (XEXP (trueop0, 0)) == mode) + && GET_MODE_INNER (GET_MODE (XEXP (trueop0, 0))) + == GET_MODE_INNER(mode)) { rtx par0 = XEXP (trueop0, 1); rtx par1 = XEXP (trueop1, 1); diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vect-rebuild.c b/gcc/testsuite/gcc.target/i386/avx512f-vect-rebuild.c new file mode 100644 index 0000000..aef6855 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-vect-rebuild.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-O -mavx512vl -mavx512dq -fno-tree-forwprop" } */ + +typedef double v2df __attribute__ ((__vector_size__ (16))); +typedef double v4df __attribute__ ((__vector_size__ (32))); + +v2df h (v4df x) +{ + v2df xx = { x[2], x[3] }; + return xx; +} + +v4df f2 (v4df x) +{ + v4df xx = { x[0], x[1], x[2], x[3] }; + return xx; +} + +/* { dg-final { scan-assembler-not "unpck" } } */ +/* { dg-final { scan-assembler-not "valign" } } */ +/* { dg-final { scan-assembler-times "\tv?extract(?:f128|f64x2)\[ \t\]" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/vect-rebuild.c b/gcc/testsuite/gcc.target/i386/vect-rebuild.c index 570967f..8e85b98 100644 --- a/gcc/testsuite/gcc.target/i386/vect-rebuild.c +++ b/gcc/testsuite/gcc.target/i386/vect-rebuild.c @@ -30,4 +30,4 @@ v2df h (v4df x) /* { dg-final { scan-assembler-not "unpck" } } */ /* { dg-final { scan-assembler-times "\tv?permilpd\[ \t\]" 1 } } */ -/* { dg-final { scan-assembler-times "\tv?extractf128\[ \t\]" 1 } } */ +/* { dg-final { scan-assembler-times "\tv?extract(?:f128|f64x2)\[ \t\]" 1 } } */ |