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authorUros Bizjak <ubizjak@gmail.com>2017-01-15 19:42:29 +0100
committerUros Bizjak <uros@gcc.gnu.org>2017-01-15 19:42:29 +0100
commit9c9a11f60d910689e387ce91a78a798e02166df3 (patch)
tree61ab25c5a2cc881941a0c070a66aa7278f6993d0 /gcc
parent81e63b637aef0fc61e85de64b2be62517723e606 (diff)
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i386.c (ix86_legitimate_combined_insn): Do not call recog here.
* config/i386/i386.c (ix86_legitimate_combined_insn): Do not call recog here. Assert that INSN_CODE (insn) is non-negative. From-SVN: r244478
Diffstat (limited to 'gcc')
-rw-r--r--gcc/ChangeLog5
-rw-r--r--gcc/config/i386/i386.c104
2 files changed, 57 insertions, 52 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9d07973..6f7d48b 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2017-01-15 Uros Bizjak <ubizjak@gmail.com>
+
+ * config/i386/i386.c (ix86_legitimate_combined_insn): Do not
+ call recog here. Assert that INSN_CODE (insn) is non-negative.
+
2017-01-15 Segher Boessenkool <segher@kernel.crashing.org>
PR target/72749
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index fc934d2..3327036 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -8125,73 +8125,73 @@ ix86_return_pops_args (tree fundecl, tree funtype, int size)
static bool
ix86_legitimate_combined_insn (rtx_insn *insn)
{
+ int i;
+
/* Check operand constraints in case hard registers were propagated
into insn pattern. This check prevents combine pass from
generating insn patterns with invalid hard register operands.
These invalid insns can eventually confuse reload to error out
with a spill failure. See also PRs 46829 and 46843. */
- if ((INSN_CODE (insn) = recog (PATTERN (insn), insn, 0)) >= 0)
- {
- int i;
- extract_insn (insn);
- preprocess_constraints (insn);
+ gcc_assert (INSN_CODE (insn) >= 0);
- int n_operands = recog_data.n_operands;
- int n_alternatives = recog_data.n_alternatives;
- for (i = 0; i < n_operands; i++)
- {
- rtx op = recog_data.operand[i];
- machine_mode mode = GET_MODE (op);
- const operand_alternative *op_alt;
- int offset = 0;
- bool win;
- int j;
+ extract_insn (insn);
+ preprocess_constraints (insn);
- /* A unary operator may be accepted by the predicate, but it
- is irrelevant for matching constraints. */
- if (UNARY_P (op))
- op = XEXP (op, 0);
+ int n_operands = recog_data.n_operands;
+ int n_alternatives = recog_data.n_alternatives;
+ for (i = 0; i < n_operands; i++)
+ {
+ rtx op = recog_data.operand[i];
+ machine_mode mode = GET_MODE (op);
+ const operand_alternative *op_alt;
+ int offset = 0;
+ bool win;
+ int j;
- if (SUBREG_P (op))
- {
- if (REG_P (SUBREG_REG (op))
- && REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER)
- offset = subreg_regno_offset (REGNO (SUBREG_REG (op)),
- GET_MODE (SUBREG_REG (op)),
- SUBREG_BYTE (op),
- GET_MODE (op));
- op = SUBREG_REG (op);
- }
+ /* A unary operator may be accepted by the predicate, but it
+ is irrelevant for matching constraints. */
+ if (UNARY_P (op))
+ op = XEXP (op, 0);
- if (!(REG_P (op) && HARD_REGISTER_P (op)))
- continue;
+ if (SUBREG_P (op))
+ {
+ if (REG_P (SUBREG_REG (op))
+ && REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER)
+ offset = subreg_regno_offset (REGNO (SUBREG_REG (op)),
+ GET_MODE (SUBREG_REG (op)),
+ SUBREG_BYTE (op),
+ GET_MODE (op));
+ op = SUBREG_REG (op);
+ }
- op_alt = recog_op_alt;
+ if (!(REG_P (op) && HARD_REGISTER_P (op)))
+ continue;
- /* Operand has no constraints, anything is OK. */
- win = !n_alternatives;
+ op_alt = recog_op_alt;
- alternative_mask preferred = get_preferred_alternatives (insn);
- for (j = 0; j < n_alternatives; j++, op_alt += n_operands)
- {
- if (!TEST_BIT (preferred, j))
- continue;
- if (op_alt[i].anything_ok
- || (op_alt[i].matches != -1
- && operands_match_p
- (recog_data.operand[i],
- recog_data.operand[op_alt[i].matches]))
- || reg_fits_class_p (op, op_alt[i].cl, offset, mode))
- {
- win = true;
- break;
- }
- }
+ /* Operand has no constraints, anything is OK. */
+ win = !n_alternatives;
- if (!win)
- return false;
+ alternative_mask preferred = get_preferred_alternatives (insn);
+ for (j = 0; j < n_alternatives; j++, op_alt += n_operands)
+ {
+ if (!TEST_BIT (preferred, j))
+ continue;
+ if (op_alt[i].anything_ok
+ || (op_alt[i].matches != -1
+ && operands_match_p
+ (recog_data.operand[i],
+ recog_data.operand[op_alt[i].matches]))
+ || reg_fits_class_p (op, op_alt[i].cl, offset, mode))
+ {
+ win = true;
+ break;
+ }
}
+
+ if (!win)
+ return false;
}
return true;