rs6000.md: Use spaces instead of tabs in output templates.

      * config/rs6000/rs6000.md: Use spaces instead of tabs in output
        templates.

From-SVN: r47059

2 files changed, 125 insertions, 120 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index aac12db..3bd66d3 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2001-11-15  Aldy Hernandez  <aldyh@redhat.com>
+
+	* config/rs6000/rs6000.md: Use spaces instead of tabs in output
+	templates.
+
 Thu Nov 15 08:36:39 2001  Richard Kenner  <kenner@vlsi1.ultra.nyu.edu>
 
 	* final.c (alter_subreg): If simplify_subreg can't do anything,
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 2fc8929..c9dfa96 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -13369,7 +13369,7 @@
   [(set (match_operand:V4SI 0 "register_operand" "=v")
 	(match_operand:V4SI 1 "memory_operand" "m"))]
   "TARGET_ALTIVEC"
-  "lvx\t%0,%y1"
+  "lvx %0,%y1"
   [(set_attr "type" "altivec")])
 
 ;; Generic STVX store instruction.
@@ -13377,7 +13377,7 @@
   [(set (match_operand:V4SI 0 "memory_operand" "=m")
 	(match_operand:V4SI 1 "register_operand" "v"))]
   "TARGET_ALTIVEC"
-  "stvx\t%1,%y0"
+  "stvx %1,%y0"
   [(set_attr "type" "altivec")])
 
 ;; Vector move instructions.
@@ -13392,9 +13392,9 @@
 	(match_operand:V4SI 1 "input_operand" "v,m,v"))]
   "TARGET_ALTIVEC"
   "@
-   stvx\t%1,%y0
-   ldvx\t%0,%y1
-   vor\t%0,%1,%1"
+   stvx %1,%y0
+   ldvx %0,%y1
+   vor %0,%1,%1"
   [(set_attr "type" "altivec")])
 
 (define_expand "movv8hi"
@@ -13408,9 +13408,9 @@
 	(match_operand:V8HI 1 "input_operand" "v,m,v"))]
   "TARGET_ALTIVEC"
   "@
-   stvx\t%1,%y0
-   ldvx\t%0,%y1
-   vor\t%0,%1,%1"
+   stvx %1,%y0
+   ldvx %0,%y1
+   vor %0,%1,%1"
   [(set_attr "type" "altivec")])
 
 (define_expand "movv16qi"
@@ -13424,9 +13424,9 @@
 	(match_operand:V16QI 1 "input_operand" "v,m,v"))]
   "TARGET_ALTIVEC"
   "@
-   stvx\t%1,%y0
-   ldvx\t%0,%y1
-   vor\t%0,%1,%1"
+   stvx %1,%y0
+   ldvx %0,%y1
+   vor %0,%1,%1"
   [(set_attr "type" "altivec")])
 
 (define_expand "movv4sf"
@@ -13440,9 +13440,9 @@
 	(match_operand:V4SF 1 "input_operand" "v,m,v"))]
   "TARGET_ALTIVEC"
   "@
-   stvx\t%1,%y0
-   ldvx\t%0,%y1
-   vor\t%0,%1,%1"
+   stvx %1,%y0
+   ldvx %0,%y1
+   vor %0,%1,%1"
   [(set_attr "type" "altivec")])
 
 ;; Simple binary operations.
@@ -13452,7 +13452,7 @@
         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
                        (match_operand:V16QI 2 "register_operand" "v")] 31))]
   "TARGET_ALTIVEC"
-  "vaddubm\t%0,%1,%2"
+  "vaddubm %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vadduhm"
@@ -13460,7 +13460,7 @@
         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
                       (match_operand:V8HI 2 "register_operand" "v")] 32))]
   "TARGET_ALTIVEC"
-  "vadduhm\t%0,%1,%2"
+  "vadduhm %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vadduwm"
@@ -13468,7 +13468,7 @@
         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
                       (match_operand:V4SI 2 "register_operand" "v")] 33))]
   "TARGET_ALTIVEC"
-  "vadduwm\t%0,%1,%2"
+  "vadduwm %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vaddfp"
@@ -13476,7 +13476,7 @@
         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
                       (match_operand:V4SF 2 "register_operand" "v")] 34))]
   "TARGET_ALTIVEC"
-  "vaddfp\t%0,%1,%2"
+  "vaddfp %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vaddcuw"
@@ -13484,7 +13484,7 @@
         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
                       (match_operand:V4SI 2 "register_operand" "v")] 35))]
   "TARGET_ALTIVEC"
-  "vaddcuw\t%0,%1,%2"
+  "vaddcuw %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vaddubs"
@@ -13492,7 +13492,7 @@
         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
                        (match_operand:V16QI 2 "register_operand" "v")] 36))]
   "TARGET_ALTIVEC"
-  "vaddubs\t%0,%1,%2"
+  "vaddubs %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vaddsbs"
@@ -13500,7 +13500,7 @@
         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
                        (match_operand:V16QI 2 "register_operand" "v")] 37))]
   "TARGET_ALTIVEC"
-  "vaddsbs\t%0,%1,%2"
+  "vaddsbs %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vadduhs"
@@ -13508,7 +13508,7 @@
         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
                       (match_operand:V8HI 2 "register_operand" "v")] 38))]
   "TARGET_ALTIVEC"
-  "vadduhs\t%0,%1,%2"
+  "vadduhs %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vaddshs"
@@ -13516,7 +13516,7 @@
         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
                       (match_operand:V8HI 2 "register_operand" "v")] 39))]
   "TARGET_ALTIVEC"
-  "vaddshs\t%0,%1,%2"
+  "vaddshs %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vadduws"
@@ -13524,7 +13524,7 @@
         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
                       (match_operand:V4SI 2 "register_operand" "v")] 40))]
   "TARGET_ALTIVEC"
-  "vadduws\t%0,%1,%2"
+  "vadduws %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vaddsws"
@@ -13532,7 +13532,7 @@
         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
                       (match_operand:V4SI 2 "register_operand" "v")] 41))]
   "TARGET_ALTIVEC"
-  "vaddsws\t%0,%1,%2"
+  "vaddsws %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vand"
@@ -13540,7 +13540,7 @@
         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
                       (match_operand:V4SI 2 "register_operand" "v")] 42))]
   "TARGET_ALTIVEC"
-  "vand\t%0,%1,%2"
+  "vand %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vandc"
@@ -13548,7 +13548,7 @@
         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
                       (match_operand:V4SI 2 "register_operand" "v")] 43))]
   "TARGET_ALTIVEC"
-  "vandc\t%0,%1,%2"
+  "vandc %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vavgub"
@@ -13556,7 +13556,7 @@
         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
                        (match_operand:V16QI 2 "register_operand" "v")] 44))]
   "TARGET_ALTIVEC"
-  "vavgub\t%0,%1,%2"
+  "vavgub %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vavgsb"
@@ -13564,7 +13564,7 @@
         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
                        (match_operand:V16QI 2 "register_operand" "v")] 45))]
   "TARGET_ALTIVEC"
-  "vavgsb\t%0,%1,%2"
+  "vavgsb %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vavguh"
@@ -13572,7 +13572,7 @@
         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
                       (match_operand:V8HI 2 "register_operand" "v")] 46))]
   "TARGET_ALTIVEC"
-  "vavguh\t%0,%1,%2"
+  "vavguh %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vavgsh"
@@ -13580,7 +13580,7 @@
         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
                       (match_operand:V8HI 2 "register_operand" "v")] 47))]
   "TARGET_ALTIVEC"
-  "vavgsh\t%0,%1,%2"
+  "vavgsh %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vavguw"
@@ -13588,7 +13588,7 @@
         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
                       (match_operand:V4SI 2 "register_operand" "v")] 48))]
   "TARGET_ALTIVEC"
-  "vavguw\t%0,%1,%2"
+  "vavguw %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vavgsw"
@@ -13596,7 +13596,7 @@
         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
                       (match_operand:V4SI 2 "register_operand" "v")] 49))]
   "TARGET_ALTIVEC"
-  "vavgsw\t%0,%1,%2"
+  "vavgsw %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vcmpbfp"
@@ -13604,7 +13604,7 @@
         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
                       (match_operand:V4SF 2 "register_operand" "v")] 50))]
   "TARGET_ALTIVEC"
-  "vcmpbfp\t%0,%1,%2"
+  "vcmpbfp %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vcmpequb"
@@ -13612,7 +13612,7 @@
         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
                        (match_operand:V16QI 2 "register_operand" "v")] 51))]
   "TARGET_ALTIVEC"
-  "vcmpequb\t%0,%1,%2"
+  "vcmpequb %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vcmpequh"
@@ -13620,7 +13620,7 @@
         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
                       (match_operand:V8HI 2 "register_operand" "v")] 52))]
   "TARGET_ALTIVEC"
-  "vcmpequh\t%0,%1,%2"
+  "vcmpequh %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vcmpequw"
@@ -13628,7 +13628,7 @@
         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
                       (match_operand:V4SI 2 "register_operand" "v")] 53))]
   "TARGET_ALTIVEC"
-  "vcmpequw\t%0,%1,%2"
+  "vcmpequw %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vcmpeqfp"
@@ -13636,7 +13636,7 @@
         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
                       (match_operand:V4SF 2 "register_operand" "v")] 54))]
   "TARGET_ALTIVEC"
-  "vcmpeqfp\t%0,%1,%2"
+  "vcmpeqfp %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vcmpgefp"
@@ -13644,7 +13644,7 @@
         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
                       (match_operand:V4SF 2 "register_operand" "v")] 55))]
   "TARGET_ALTIVEC"
-  "vcmpgefp\t%0,%1,%2"
+  "vcmpgefp %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vcmpgtub"
@@ -13652,7 +13652,7 @@
         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
                        (match_operand:V16QI 2 "register_operand" "v")] 56))]
   "TARGET_ALTIVEC"
-  "vcmpgtub\t%0,%1,%2"
+  "vcmpgtub %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vcmpgtsb"
@@ -13660,7 +13660,7 @@
         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
                        (match_operand:V16QI 2 "register_operand" "v")] 57))]
   "TARGET_ALTIVEC"
-  "vcmpgtsb\t%0,%1,%2"
+  "vcmpgtsb %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vcmpgtuh"
@@ -13668,7 +13668,7 @@
         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
                       (match_operand:V8HI 2 "register_operand" "v")] 58))]
   "TARGET_ALTIVEC"
-  "vcmpgtuh\t%0,%1,%2"
+  "vcmpgtuh %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vcmpgtsh"
@@ -13676,7 +13676,7 @@
         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
                       (match_operand:V8HI 2 "register_operand" "v")] 59))]
   "TARGET_ALTIVEC"
-  "vcmpgtsh\t%0,%1,%2"
+  "vcmpgtsh %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vcmpgtuw"
@@ -13684,7 +13684,7 @@
         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
                       (match_operand:V4SI 2 "register_operand" "v")] 60))]
   "TARGET_ALTIVEC"
-  "vcmpgtuw\t%0,%1,%2"
+  "vcmpgtuw %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vcmpgtsw"
@@ -13692,7 +13692,7 @@
         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
                       (match_operand:V4SI 2 "register_operand" "v")] 61))]
   "TARGET_ALTIVEC"
-  "vcmpgtsw\t%0,%1,%2"
+  "vcmpgtsw %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vcmpgtfp"
@@ -13700,7 +13700,7 @@
         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
                       (match_operand:V4SF 2 "register_operand" "v")] 62))]
   "TARGET_ALTIVEC"
-  "vcmpgtfp\t%0,%1,%2"
+  "vcmpgtfp %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vmaxub"
@@ -13708,7 +13708,7 @@
         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
                        (match_operand:V16QI 2 "register_operand" "v")] 63))]
   "TARGET_ALTIVEC"
-  "vmaxub\t%0,%1,%2"
+  "vmaxub %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vmaxsb"
@@ -13716,7 +13716,7 @@
         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
                        (match_operand:V16QI 2 "register_operand" "v")] 64))]
   "TARGET_ALTIVEC"
-  "vmaxsb\t%0,%1,%2"
+  "vmaxsb %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vmaxuh"
@@ -13724,7 +13724,7 @@
         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
                       (match_operand:V8HI 2 "register_operand" "v")] 65))]
   "TARGET_ALTIVEC"
-  "vmaxuh\t%0,%1,%2"
+  "vmaxuh %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vmaxsh"
@@ -13732,7 +13732,7 @@
         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
                       (match_operand:V8HI 2 "register_operand" "v")] 66))]
   "TARGET_ALTIVEC"
-  "vmaxsh\t%0,%1,%2"
+  "vmaxsh %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vmaxuw"
@@ -13740,7 +13740,7 @@
         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
                       (match_operand:V4SI 2 "register_operand" "v")] 67))]
   "TARGET_ALTIVEC"
-  "vmaxuw\t%0,%1,%2"
+  "vmaxuw %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vmaxsw"
@@ -13748,7 +13748,7 @@
         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
                       (match_operand:V4SI 2 "register_operand" "v")] 68))]
   "TARGET_ALTIVEC"
-  "vmaxsw\t%0,%1,%2"
+  "vmaxsw %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vmaxfp"
@@ -13756,7 +13756,7 @@
         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
                       (match_operand:V4SF 2 "register_operand" "v")] 69))]
   "TARGET_ALTIVEC"
-  "vmaxfp\t%0,%1,%2"
+  "vmaxfp %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vmrghb"
@@ -13764,7 +13764,7 @@
         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
                        (match_operand:V16QI 2 "register_operand" "v")] 70))]
   "TARGET_ALTIVEC"
-  "vmrghb\t%0,%1,%2"
+  "vmrghb %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vmrghh"
@@ -13772,7 +13772,7 @@
         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
                       (match_operand:V8HI 2 "register_operand" "v")] 71))]
   "TARGET_ALTIVEC"
-  "vmrghh\t%0,%1,%2"
+  "vmrghh %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vmrghw"
@@ -13780,7 +13780,7 @@
         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
                       (match_operand:V4SI 2 "register_operand" "v")] 72))]
   "TARGET_ALTIVEC"
-  "vmrghw\t%0,%1,%2"
+  "vmrghw %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vmrglb"
@@ -13788,7 +13788,7 @@
         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
                        (match_operand:V16QI 2 "register_operand" "v")] 73))]
   "TARGET_ALTIVEC"
-  "vmrglb\t%0,%1,%2"
+  "vmrglb %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vmrglh"
@@ -13796,7 +13796,7 @@
         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
                       (match_operand:V8HI 2 "register_operand" "v")] 74))]
   "TARGET_ALTIVEC"
-  "vmrglh\t%0,%1,%2"
+  "vmrglh %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vmrglw"
@@ -13804,7 +13804,7 @@
         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
                       (match_operand:V4SI 2 "register_operand" "v")] 75))]
   "TARGET_ALTIVEC"
-  "vmrglw\t%0,%1,%2"
+  "vmrglw %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vminub"
@@ -13812,7 +13812,7 @@
         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
                        (match_operand:V16QI 2 "register_operand" "v")] 76))]
   "TARGET_ALTIVEC"
-  "vminub\t%0,%1,%2"
+  "vminub %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vminsb"
@@ -13820,7 +13820,7 @@
         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
                        (match_operand:V16QI 2 "register_operand" "v")] 77))]
   "TARGET_ALTIVEC"
-  "vminsb\t%0,%1,%2"
+  "vminsb %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vminuh"
@@ -13828,7 +13828,7 @@
         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
                       (match_operand:V8HI 2 "register_operand" "v")] 78))]
   "TARGET_ALTIVEC"
-  "vminuh\t%0,%1,%2"
+  "vminuh %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vminsh"
@@ -13836,7 +13836,7 @@
         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
                       (match_operand:V8HI 2 "register_operand" "v")] 79))]
   "TARGET_ALTIVEC"
-  "vminsh\t%0,%1,%2"
+  "vminsh %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vminuw"
@@ -13844,7 +13844,7 @@
         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
                       (match_operand:V4SI 2 "register_operand" "v")] 80))]
   "TARGET_ALTIVEC"
-  "vminuw\t%0,%1,%2"
+  "vminuw %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vminsw"
@@ -13852,7 +13852,7 @@
         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
                       (match_operand:V4SI 2 "register_operand" "v")] 81))]
   "TARGET_ALTIVEC"
-  "vminsw\t%0,%1,%2"
+  "vminsw %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vminfp"
@@ -13860,7 +13860,7 @@
         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
                       (match_operand:V4SF 2 "register_operand" "v")] 82))]
   "TARGET_ALTIVEC"
-  "vminfp\t%0,%1,%2"
+  "vminfp %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vmuleub"
@@ -13868,7 +13868,7 @@
         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
                       (match_operand:V16QI 2 "register_operand" "v")] 83))]
   "TARGET_ALTIVEC"
-  "vmuleub\t%0,%1,%2"
+  "vmuleub %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vmulesb"
@@ -13876,7 +13876,7 @@
         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
                       (match_operand:V16QI 2 "register_operand" "v")] 84))]
   "TARGET_ALTIVEC"
-  "vmulesb\t%0,%1,%2"
+  "vmulesb %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vmuleuh"
@@ -13884,7 +13884,7 @@
         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
                       (match_operand:V8HI 2 "register_operand" "v")] 85))]
   "TARGET_ALTIVEC"
-  "vmuleuh\t%0,%1,%2"
+  "vmuleuh %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vmulesh"
@@ -13892,7 +13892,7 @@
         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
                       (match_operand:V8HI 2 "register_operand" "v")] 86))]
   "TARGET_ALTIVEC"
-  "vmulesh\t%0,%1,%2"
+  "vmulesh %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vmuloub"
@@ -13900,7 +13900,7 @@
         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
                       (match_operand:V16QI 2 "register_operand" "v")] 87))]
   "TARGET_ALTIVEC"
-  "vmuloub\t%0,%1,%2"
+  "vmuloub %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vmulosb"
@@ -13908,7 +13908,7 @@
         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
                       (match_operand:V16QI 2 "register_operand" "v")] 88))]
   "TARGET_ALTIVEC"
-  "vmulosb\t%0,%1,%2"
+  "vmulosb %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vmulouh"
@@ -13916,7 +13916,7 @@
         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
                       (match_operand:V8HI 2 "register_operand" "v")] 89))]
   "TARGET_ALTIVEC"
-  "vmulouh\t%0,%1,%2"
+  "vmulouh %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vmulosh"
@@ -13924,7 +13924,7 @@
         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
                       (match_operand:V8HI 2 "register_operand" "v")] 90))]
   "TARGET_ALTIVEC"
-  "vmulosh\t%0,%1,%2"
+  "vmulosh %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vnor"
@@ -13932,7 +13932,7 @@
         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
                       (match_operand:V4SI 2 "register_operand" "v")] 91))]
   "TARGET_ALTIVEC"
-  "vnor\t%0,%1,%2"
+  "vnor %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vor"
@@ -13940,7 +13940,7 @@
         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
                       (match_operand:V4SI 2 "register_operand" "v")] 92))]
   "TARGET_ALTIVEC"
-  "vor\t%0,%1,%2"
+  "vor %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vpkuhum"
@@ -13948,7 +13948,7 @@
         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
                        (match_operand:V8HI 2 "register_operand" "v")] 93))]
   "TARGET_ALTIVEC"
-  "vpkuhum\t%0,%1,%2"
+  "vpkuhum %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vpkuwum"
@@ -13956,7 +13956,7 @@
         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
                       (match_operand:V4SI 2 "register_operand" "v")] 94))]
   "TARGET_ALTIVEC"
-  "vpkuwum\t%0,%1,%2"
+  "vpkuwum %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vpkpx"
@@ -13964,7 +13964,7 @@
         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
                       (match_operand:V4SI 2 "register_operand" "v")] 95))]
   "TARGET_ALTIVEC"
-  "vpkpx\t%0,%1,%2"
+  "vpkpx %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vpkuhss"
@@ -13972,7 +13972,7 @@
         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
                        (match_operand:V8HI 2 "register_operand" "v")] 96))]
   "TARGET_ALTIVEC"
-  "vpkuhss\t%0,%1,%2"
+  "vpkuhss %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vpkshss"
@@ -13980,7 +13980,7 @@
         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
                        (match_operand:V8HI 2 "register_operand" "v")] 97))]
   "TARGET_ALTIVEC"
-  "vpkshss\t%0,%1,%2"
+  "vpkshss %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vpkuwss"
@@ -13988,7 +13988,7 @@
         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
                       (match_operand:V4SI 2 "register_operand" "v")] 98))]
   "TARGET_ALTIVEC"
-  "vpkuwss\t%0,%1,%2"
+  "vpkuwss %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vpkswss"
@@ -13996,7 +13996,7 @@
         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
                       (match_operand:V4SI 2 "register_operand" "v")] 99))]
   "TARGET_ALTIVEC"
-  "vpkswss\t%0,%1,%2"
+  "vpkswss %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vpkuhus"
@@ -14004,7 +14004,7 @@
         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
                        (match_operand:V8HI 2 "register_operand" "v")] 100))]
   "TARGET_ALTIVEC"
-  "vpkuhus\t%0,%1,%2"
+  "vpkuhus %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vpkshus"
@@ -14012,7 +14012,7 @@
         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
                        (match_operand:V8HI 2 "register_operand" "v")] 101))]
   "TARGET_ALTIVEC"
-  "vpkshus\t%0,%1,%2"
+  "vpkshus %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vpkuwus"
@@ -14020,7 +14020,7 @@
         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
                       (match_operand:V4SI 2 "register_operand" "v")] 102))]
   "TARGET_ALTIVEC"
-  "vpkuwus\t%0,%1,%2"
+  "vpkuwus %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vpkswus"
@@ -14028,7 +14028,7 @@
         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
                       (match_operand:V4SI 2 "register_operand" "v")] 103))]
   "TARGET_ALTIVEC"
-  "vpkswus\t%0,%1,%2"
+  "vpkswus %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vrlb"
@@ -14036,7 +14036,7 @@
         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
                        (match_operand:V16QI 2 "register_operand" "v")] 104))]
   "TARGET_ALTIVEC"
-  "vrlb\t%0,%1,%2"
+  "vrlb %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vrlh"
@@ -14044,7 +14044,7 @@
         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
                       (match_operand:V8HI 2 "register_operand" "v")] 105))]
   "TARGET_ALTIVEC"
-  "vrlh\t%0,%1,%2"
+  "vrlh %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vrlw"
@@ -14052,7 +14052,7 @@
         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
                       (match_operand:V4SI 2 "register_operand" "v")] 106))]
   "TARGET_ALTIVEC"
-  "vrlw\t%0,%1,%2"
+  "vrlw %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vslb"
@@ -14060,7 +14060,7 @@
         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
                        (match_operand:V16QI 2 "register_operand" "v")] 107))]
   "TARGET_ALTIVEC"
-  "vslb\t%0,%1,%2"
+  "vslb %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vslh"
@@ -14068,7 +14068,7 @@
         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
                       (match_operand:V8HI 2 "register_operand" "v")] 108))]
   "TARGET_ALTIVEC"
-  "vslh\t%0,%1,%2"
+  "vslh %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vslw"
@@ -14076,7 +14076,7 @@
         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
                       (match_operand:V4SI 2 "register_operand" "v")] 109))]
   "TARGET_ALTIVEC"
-  "vslw\t%0,%1,%2"
+  "vslw %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vsl"
@@ -14084,7 +14084,7 @@
         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
                       (match_operand:V4SI 2 "register_operand" "v")] 110))]
   "TARGET_ALTIVEC"
-  "vsl\t%0,%1,%2"
+  "vsl %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vslo"
@@ -14092,7 +14092,7 @@
         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
                       (match_operand:V4SI 2 "register_operand" "v")] 111))]
   "TARGET_ALTIVEC"
-  "vslo\t%0,%1,%2"
+  "vslo %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vsrb"
@@ -14100,7 +14100,7 @@
         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
                        (match_operand:V16QI 2 "register_operand" "v")] 112))]
   "TARGET_ALTIVEC"
-  "vsrb\t%0,%1,%2"
+  "vsrb %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vrsh"
@@ -14108,7 +14108,7 @@
         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
                       (match_operand:V8HI 2 "register_operand" "v")] 113))]
   "TARGET_ALTIVEC"
-  "vrsh\t%0,%1,%2"
+  "vrsh %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vrsw"
@@ -14116,7 +14116,7 @@
         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
                       (match_operand:V4SI 2 "register_operand" "v")] 114))]
   "TARGET_ALTIVEC"
-  "vrsw\t%0,%1,%2"
+  "vrsw %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vsrab"
@@ -14124,7 +14124,7 @@
         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
                        (match_operand:V16QI 2 "register_operand" "v")] 115))]
   "TARGET_ALTIVEC"
-  "vsrab\t%0,%1,%2"
+  "vsrab %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vsrah"
@@ -14132,7 +14132,7 @@
         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
                       (match_operand:V8HI 2 "register_operand" "v")] 116))]
   "TARGET_ALTIVEC"
-  "vsrah\t%0,%1,%2"
+  "vsrah %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vsraw"
@@ -14140,7 +14140,7 @@
         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
                       (match_operand:V4SI 2 "register_operand" "v")] 117))]
   "TARGET_ALTIVEC"
-  "vsraw\t%0,%1,%2"
+  "vsraw %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vsr"
@@ -14148,7 +14148,7 @@
         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
                       (match_operand:V4SI 2 "register_operand" "v")] 118))]
   "TARGET_ALTIVEC"
-  "vsr\t%0,%1,%2"
+  "vsr %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vsro"
@@ -14156,7 +14156,7 @@
         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
                       (match_operand:V4SI 2 "register_operand" "v")] 119))]
   "TARGET_ALTIVEC"
-  "vsro\t%0,%1,%2"
+  "vsro %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vsububm"
@@ -14164,7 +14164,7 @@
         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
                        (match_operand:V16QI 2 "register_operand" "v")] 120))]
   "TARGET_ALTIVEC"
-  "vsububm\t%0,%1,%2"
+  "vsububm %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vsubuhm"
@@ -14172,7 +14172,7 @@
         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
                       (match_operand:V8HI 2 "register_operand" "v")] 121))]
   "TARGET_ALTIVEC"
-  "vsubuhm\t%0,%1,%2"
+  "vsubuhm %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vsubuwm"
@@ -14180,7 +14180,7 @@
         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
                       (match_operand:V4SI 2 "register_operand" "v")] 122))]
   "TARGET_ALTIVEC"
-  "vsubuwm\t%0,%1,%2"
+  "vsubuwm %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vsubfp"
@@ -14188,7 +14188,7 @@
         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
                       (match_operand:V4SF 2 "register_operand" "v")] 123))]
   "TARGET_ALTIVEC"
-  "vsubfp\t%0,%1,%2"
+  "vsubfp %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vsubcuw"
@@ -14196,7 +14196,7 @@
         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
                       (match_operand:V4SI 2 "register_operand" "v")] 124))]
   "TARGET_ALTIVEC"
-  "vsubcuw\t%0,%1,%2"
+  "vsubcuw %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vsububs"
@@ -14204,7 +14204,7 @@
         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
                        (match_operand:V16QI 2 "register_operand" "v")] 125))]
   "TARGET_ALTIVEC"
-  "vsububs\t%0,%1,%2"
+  "vsububs %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vsubsbs"
@@ -14212,7 +14212,7 @@
         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
                        (match_operand:V16QI 2 "register_operand" "v")] 126))]
   "TARGET_ALTIVEC"
-  "vsubsbs\t%0,%1,%2"
+  "vsubsbs %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vsubuhs"
@@ -14220,7 +14220,7 @@
         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
                       (match_operand:V8HI 2 "register_operand" "v")] 127))]
   "TARGET_ALTIVEC"
-  "vsubuhs\t%0,%1,%2"
+  "vsubuhs %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vsubshs"
@@ -14228,7 +14228,7 @@
         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
                       (match_operand:V8HI 2 "register_operand" "v")] 128))]
   "TARGET_ALTIVEC"
-  "vsubshs\t%0,%1,%2"
+  "vsubshs %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vsubuws"
@@ -14236,7 +14236,7 @@
         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
                       (match_operand:V4SI 2 "register_operand" "v")] 129))]
   "TARGET_ALTIVEC"
-  "vsubuws\t%0,%1,%2"
+  "vsubuws %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vsubsws"
@@ -14244,7 +14244,7 @@
         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
                       (match_operand:V4SI 2 "register_operand" "v")] 130))]
   "TARGET_ALTIVEC"
-  "vsubsws\t%0,%1,%2"
+  "vsubsws %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vsum4ubs"
@@ -14252,7 +14252,7 @@
         (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
                       (match_operand:V4SI 2 "register_operand" "v")] 131))]
   "TARGET_ALTIVEC"
-  "vsum4ubs\t%0,%1,%2"
+  "vsum4ubs %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vsum4sbs"
@@ -14260,7 +14260,7 @@
         (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
                       (match_operand:V4SI 2 "register_operand" "v")] 132))]
   "TARGET_ALTIVEC"
-  "vsum4sbs\t%0,%1,%2"
+  "vsum4sbs %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vsum4shs"
@@ -14268,7 +14268,7 @@
         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
                       (match_operand:V4SI 2 "register_operand" "v")] 133))]
   "TARGET_ALTIVEC"
-  "vsum4shs\t%0,%1,%2"
+  "vsum4shs %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vsum2sws"
@@ -14276,7 +14276,7 @@
         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
                       (match_operand:V4SI 2 "register_operand" "v")] 134))]
   "TARGET_ALTIVEC"
-  "vsum2sws\t%0,%1,%2"
+  "vsum2sws %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vsumsws"
@@ -14284,7 +14284,7 @@
         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
                       (match_operand:V4SI 2 "register_operand" "v")] 135))]
   "TARGET_ALTIVEC"
-  "vsumsws\t%0,%1,%2"
+  "vsumsws %0,%1,%2"
   [(set_attr "type" "altivec")])
 
 (define_insn "altivec_vxor"
@@ -14292,5 +14292,5 @@
         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
                       (match_operand:V4SI 2 "register_operand" "v")] 136))]
   "TARGET_ALTIVEC"
-  "vxor\t%0,%1,%2"
+  "vxor %0,%1,%2"
   [(set_attr "type" "altivec")])