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| author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | 2023-09-15 17:03:49 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-09-15 19:08:30 +0800 |
| commit | 9b80311cdc685e6f27cf4f8625ac3d24dcc59d7f (patch) | |
| tree | 18beccada6f52641c2698f84927c43b39cb0f3f2 /gcc | |
| parent | 0854ebea63f59eb678ebf4440afe1d18ed5bb6d4 (diff) | |
| download | gcc-9b80311cdc685e6f27cf4f8625ac3d24dcc59d7f.zip gcc-9b80311cdc685e6f27cf4f8625ac3d24dcc59d7f.tar.gz gcc-9b80311cdc685e6f27cf4f8625ac3d24dcc59d7f.tar.bz2 | |
test: Block slp-16.c check for target support vect_strided6
This testcase FAIL in RISC-V because RISC-V support vect_load_lanes with 6.
FAIL: gcc.dg/vect/slp-16.c -flto -ffat-lto-objects scan-tree-dump-times vect "vectorizing stmts using SLP" 2
FAIL: gcc.dg/vect/slp-16.c scan-tree-dump-times vect "vectorizing stmts using SLP" 2
Since it use vlseg6 (vect_load_lanes with array size = 6)
gcc/testsuite/ChangeLog:
* gcc.dg/vect/slp-16.c: Block vect_strided6.
* lib/target-supports.exp: Add strided type.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/testsuite/gcc.dg/vect/slp-16.c | 2 | ||||
| -rw-r--r-- | gcc/testsuite/lib/target-supports.exp | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/gcc/testsuite/gcc.dg/vect/slp-16.c b/gcc/testsuite/gcc.dg/vect/slp-16.c index d053a64..44ba730 100644 --- a/gcc/testsuite/gcc.dg/vect/slp-16.c +++ b/gcc/testsuite/gcc.dg/vect/slp-16.c @@ -67,5 +67,5 @@ int main (void) } /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_int_mult } } } */ -/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" { target vect_int_mult } } } */ +/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" { target { vect_int_mult && {! vect_strided6 } } } } } */ diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index edaa010..2de41ce 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -8621,7 +8621,7 @@ proc check_effective_target_vect_interleave { } { && [check_effective_target_s390_vx]) }}] } -foreach N {2 3 4 8} { +foreach N {2 3 4 5 6 7 8} { eval [string map [list N $N] { # Return 1 if the target supports 2-vector interleaving proc check_effective_target_vect_stridedN { } { |