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| author | Sinan Lin <sinan.lin@linux.alibaba.com> | 2023-04-18 12:24:52 -0600 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro> | 2023-04-18 12:27:08 -0600 |
| commit | 9874ceed091a0ce17b23d8d77b5bf90b8902a3c0 (patch) | |
| tree | aa02a4bfc9dc3a137cc0576975d00e31825ceeb5 /gcc | |
| parent | 95b99e47f4f2df2d0c5680f45e3ec0a3170218ad (diff) | |
| download | gcc-9874ceed091a0ce17b23d8d77b5bf90b8902a3c0.zip gcc-9874ceed091a0ce17b23d8d77b5bf90b8902a3c0.tar.gz gcc-9874ceed091a0ce17b23d8d77b5bf90b8902a3c0.tar.bz2 | |
Add TARGET_ZBKB to the condition of bswapsi2, bswapdi2 and rotr<mode>3 patterns
gcc/
* config/riscv/bitmanip.md (rotr<mode>3 expander): Enable for ZBKB.
(bswapdi2, bswapsi2): Similarly.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/riscv/bitmanip.md | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index 062968d..388ef66 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -297,7 +297,7 @@ [(set (match_operand:GPR 0 "register_operand") (rotatert:GPR (match_operand:GPR 1 "register_operand") (match_operand:QI 2 "arith_operand")))] - "TARGET_ZBB || TARGET_XTHEADBB" + "TARGET_ZBB || TARGET_XTHEADBB || TARGET_ZBKB" { if (TARGET_XTHEADBB && !immediate_operand (operands[2], VOIDmode)) FAIL; @@ -362,12 +362,12 @@ (define_expand "bswapdi2" [(set (match_operand:DI 0 "register_operand") (bswap:DI (match_operand:DI 1 "register_operand")))] - "TARGET_64BIT && (TARGET_ZBB || TARGET_XTHEADBB)") + "TARGET_64BIT && (TARGET_ZBB || TARGET_XTHEADBB || TARGET_ZBKB)") (define_expand "bswapsi2" [(set (match_operand:SI 0 "register_operand") (bswap:SI (match_operand:SI 1 "register_operand")))] - "(!TARGET_64BIT && TARGET_ZBB) || TARGET_XTHEADBB") + "(!TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)) || TARGET_XTHEADBB") (define_insn "*bswap<mode>2" [(set (match_operand:X 0 "register_operand" "=r") |