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| author | liuhongt <hongtao.liu@intel.com> | 2021-06-24 16:14:13 +0800 |
|---|---|---|
| committer | liuhongt <hongtao.liu@intel.com> | 2021-06-25 09:17:18 +0800 |
| commit | 980e278dbe5b50dc5a856ea627359c521f1cda53 (patch) | |
| tree | d796a9dd35fefb21c37d5667f330d8fe22870b78 /gcc | |
| parent | 9aa8327e86eba9a5ad6dacb4db505e3451854976 (diff) | |
| download | gcc-980e278dbe5b50dc5a856ea627359c521f1cda53.zip gcc-980e278dbe5b50dc5a856ea627359c521f1cda53.tar.gz gcc-980e278dbe5b50dc5a856ea627359c521f1cda53.tar.bz2 | |
Revert x86_order_regs_for_local_alloc changes in r12-1669.
Still put general regs as first alloca order.
gcc/ChangeLog:
PR target/101185
* config/i386/i386.c (x86_order_regs_for_local_alloc):
Revert r12-1669.
gcc/testsuite/ChangeLog
PR target/101185
* gcc.target/i386/bitwise_mask_op-3.c: Add xfail to
temporarily avoid regression, eventually xfail should be
removed.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/i386/i386.c | 13 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/bitwise_mask_op-3.c | 6 |
2 files changed, 7 insertions, 12 deletions
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 3d5883b..c71c9e6 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -20476,15 +20476,6 @@ x86_order_regs_for_local_alloc (void) int pos = 0; int i; - /* When allocano cost of GENERAL_REGS is same as MASK_REGS, allocate - MASK_REGS first since it has already been disparaged. This is for - testcase bitwise_mask_op3.c where the input is allocated as mask - registers, then mask bitwise instructions should be used there. - Refer to pr101142. */ - /* Mask register. */ - for (i = FIRST_MASK_REG; i <= LAST_MASK_REG; i++) - reg_alloc_order [pos++] = i; - /* First allocate the local general purpose registers. */ for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) if (GENERAL_REGNO_P (i) && call_used_or_fixed_reg_p (i)) @@ -20511,6 +20502,10 @@ x86_order_regs_for_local_alloc (void) for (i = FIRST_EXT_REX_SSE_REG; i <= LAST_EXT_REX_SSE_REG; i++) reg_alloc_order [pos++] = i; + /* Mask register. */ + for (i = FIRST_MASK_REG; i <= LAST_MASK_REG; i++) + reg_alloc_order [pos++] = i; + /* x87 registers. */ if (TARGET_SSE_MATH) for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++) diff --git a/gcc/testsuite/gcc.target/i386/bitwise_mask_op-3.c b/gcc/testsuite/gcc.target/i386/bitwise_mask_op-3.c index 4a90786..352c49d 100644 --- a/gcc/testsuite/gcc.target/i386/bitwise_mask_op-3.c +++ b/gcc/testsuite/gcc.target/i386/bitwise_mask_op-3.c @@ -12,7 +12,7 @@ foo_orb (__m512i a, __m512i b) foo = m1 | m2; } -/* { dg-final { scan-assembler-times "korb\[\t \]" "1" } } */ +/* { dg-final { scan-assembler-times "korb\[\t \]" "1" { xfail *-*-* } } } */ void foo_xorb (__m512i a, __m512i b) @@ -22,7 +22,7 @@ foo_xorb (__m512i a, __m512i b) foo = m1 ^ m2; } -/* { dg-final { scan-assembler-times "kxorb\[\t \]" "1" } } */ +/* { dg-final { scan-assembler-times "kxorb\[\t \]" "1" { xfail *-*-* } } } */ void foo_andb (__m512i a, __m512i b) @@ -40,4 +40,4 @@ foo_andnb (__m512i a, __m512i b) foo = m1 & ~m2; } -/* { dg-final { scan-assembler-times "kmovb\[\t \]" "4"} } */ +/* { dg-final { scan-assembler-times "kmovb\[\t \]" "4" { xfail *-*-* } } } */ |