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| author | Richard Henderson <rth@redhat.com> | 2011-10-07 14:07:10 -0700 |
|---|---|---|
| committer | Richard Henderson <rth@gcc.gnu.org> | 2011-10-07 14:07:10 -0700 |
| commit | 96d861154f434b52a80c71c6a4e0d69ebf609be1 (patch) | |
| tree | 1e27407511fc3cee5c2af4b022f81ec6374b5404 /gcc | |
| parent | 621babd8d07859054fb78b9ca4fa97ffd4fd5c0e (diff) | |
| download | gcc-96d861154f434b52a80c71c6a4e0d69ebf609be1.zip gcc-96d861154f434b52a80c71c6a4e0d69ebf609be1.tar.gz gcc-96d861154f434b52a80c71c6a4e0d69ebf609be1.tar.bz2 | |
i386: Fix representation of 256-bit vpblendw.
From-SVN: r179697
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/i386/predicates.md | 9 | ||||
| -rw-r--r-- | gcc/config/i386/sse.md | 42 |
3 files changed, 51 insertions, 6 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f3544a2..128072f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,11 @@ 2011-10-07 Richard Henderson <rth@redhat.com> + * config/i386/predicates.md (avx2_pblendw_operand): New. + * config/i386/sse.md (sse4_1_pblendw): Un-macroize. + (avx2_pblendw, *avx2_pblendw): New expander and insn. + +2011-10-07 Richard Henderson <rth@redhat.com> + * config/i386/i386.c (bdesc_args): Update code for __builtin_ia32_palignr256. Change type of __builtin_ia32_pslldqi256, and __builtin_ia32_psrldqi256 to V4DI_FTYPE_V4DI_INT_CONVERT. diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md index 89cc8a7..9ac3f9d 100644 --- a/gcc/config/i386/predicates.md +++ b/gcc/config/i386/predicates.md @@ -1210,3 +1210,12 @@ return false; return true; }) + +;; Return true if OP is a proper third operand to vpblendw256. +(define_predicate "avx2_pblendw_operand" + (match_code "const_int") +{ + HOST_WIDE_INT val = INTVAL (op); + HOST_WIDE_INT low = val & 0xff; + return val == (low << 8) | low; +}) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index a7df221..9dc9b46 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -9417,11 +9417,11 @@ (set_attr "prefix" "orig,vex") (set_attr "mode" "<sseinsnmode>")]) -(define_insn "<sse4_1_avx2>_pblendw" - [(set (match_operand:VI2_AVX2 0 "register_operand" "=x,x") - (vec_merge:VI2_AVX2 - (match_operand:VI2_AVX2 2 "nonimmediate_operand" "xm,xm") - (match_operand:VI2_AVX2 1 "register_operand" "0,x") +(define_insn "sse4_1_pblendw" + [(set (match_operand:V8HI 0 "register_operand" "=x,x") + (vec_merge:V8HI + (match_operand:V8HI 2 "nonimmediate_operand" "xm,xm") + (match_operand:V8HI 1 "register_operand" "0,x") (match_operand:SI 3 "const_0_to_255_operand" "n,n")))] "TARGET_SSE4_1" "@ @@ -9432,7 +9432,37 @@ (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "prefix" "orig,vex") - (set_attr "mode" "<sseinsnmode>")]) + (set_attr "mode" "TI")]) + +;; The builtin uses an 8-bit immediate. Expand that. +(define_expand "avx2_pblendw" + [(set (match_operand:V16HI 0 "register_operand" "") + (vec_merge:V16HI + (match_operand:V16HI 2 "nonimmediate_operand" "") + (match_operand:V16HI 1 "register_operand" "") + (match_operand:SI 3 "const_0_to_255_operand" "")))] + "TARGET_AVX2" +{ + HOST_WIDE_INT val = INTVAL (operands[3]) & 0xff; + operands[3] = GEN_INT (val << 8 | val); +}) + +(define_insn "*avx2_pblendw" + [(set (match_operand:V16HI 0 "register_operand" "=x") + (vec_merge:V16HI + (match_operand:V16HI 2 "nonimmediate_operand" "xm") + (match_operand:V16HI 1 "register_operand" "x") + (match_operand:SI 3 "avx2_pblendw_operand" "n")))] + "TARGET_SSE4_1" +{ + operands[3] = GEN_INT (INTVAL (operands[3]) & 0xff); + return "vpblendw\t{%3, %2, %1, %0|%0, %1, %2, %3}"; +} + [(set_attr "type" "ssemov") + (set_attr "prefix_extra" "1") + (set_attr "length_immediate" "1") + (set_attr "prefix" "vex") + (set_attr "mode" "OI")]) (define_insn "avx2_pblendd<mode>" [(set (match_operand:VI4_AVX2 0 "register_operand" "=x") |