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| author | Pan Li <pan2.li@intel.com> | 2023-06-13 15:13:48 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-06-13 15:26:34 +0800 |
| commit | 95e2a51685d5ce977c332735ddc5ef39e777639e (patch) | |
| tree | 435bc6943038b99cc5877bf1e7a650009d2c3020 /gcc | |
| parent | 22d85c10a004f4f5eaf6b68b62a0792faf048bf8 (diff) | |
| download | gcc-95e2a51685d5ce977c332735ddc5ef39e777639e.zip gcc-95e2a51685d5ce977c332735ddc5ef39e777639e.tar.gz gcc-95e2a51685d5ce977c332735ddc5ef39e777639e.tar.bz2 | |
RISC-V: Fix one typo in full-vec-movel test
This patch would like to fix one typo when checking assembly of
full-vec-movel.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c:
Adjust dg-do to comiple for asm checking.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c index c1119cd..c32c31e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_vector } } } */ +/* { dg-do compile } */ /* { dg-additional-options "-std=c99 -O3 -march=rv64gcv_zvl128b -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ #include <stdint-gcc.h> |