diff options
author | Ju-Zhe Zhong <juzhe.zhong@rivai.ai> | 2023-01-03 09:39:57 +0800 |
---|---|---|
committer | Kito Cheng <kito.cheng@sifive.com> | 2023-01-27 02:53:00 +0800 |
commit | 91a41201b5cea1d72cd84e0e8751289774fcba42 (patch) | |
tree | 649e328840235e23bfcd3a3cc45d2d53b33f51d8 /gcc | |
parent | 856eec0d6b65c7b28b4b6c4fd6ccc10f2f6a22b1 (diff) | |
download | gcc-91a41201b5cea1d72cd84e0e8751289774fcba42.zip gcc-91a41201b5cea1d72cd84e0e8751289774fcba42.tar.gz gcc-91a41201b5cea1d72cd84e0e8751289774fcba42.tar.bz2 |
RISC-V: Fix vsetivli instruction asm for IMM AVL
Notice that we should used vsetivli zero,4 instead of vsetvli zero,4
for IMM AVL (0 ~ 31) according to RVV ISA.
This patch fix vsetivli instruction asm bug.
gcc/ChangeLog:
* config/riscv/vector.md:
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vle-constraint-1.c:
Diffstat (limited to 'gcc')
-rw-r--r-- | gcc/config/riscv/vector.md | 2 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/base/vle-constraint-1.c | 12 |
2 files changed, 7 insertions, 7 deletions
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 1ec0a4d..83bc1ab 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -581,7 +581,7 @@ (match_operand 3 "const_int_operand" "i") (match_operand 4 "const_int_operand" "i")] UNSPEC_VSETVL))] "TARGET_VECTOR" - "vsetvli\tzero,%0,e%1,%m2,t%p3,m%p4" + "vset%i0vli\tzero,%0,e%1,%m2,t%p3,m%p4" [(set_attr "type" "vsetvl") (set_attr "mode" "<MODE>")]) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vle-constraint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vle-constraint-1.c index b7cf98b..8d01e20 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/vle-constraint-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vle-constraint-1.c @@ -6,7 +6,7 @@ /* ** f1: -** vsetvli\tzero,4,e32,m1,tu,ma +** vsetivli\tzero,4,e32,m1,tu,ma ** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) ** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) ** vse32\.v\tv[0-9]+,0\([a-x0-9]+\) @@ -23,7 +23,7 @@ void f1 (float * in, float *out) ** f2: ** vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma ** vlm.v\tv[0-9]+,0\([a-x0-9]+\) -** vsetvli\tzero,4,e32,m1,ta,ma +** vsetivli\tzero,4,e32,m1,ta,ma ** vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t ** vse32.v\tv[0-9]+,0\([a-x0-9]+\) ** ret @@ -41,7 +41,7 @@ void f2 (float * in, float *out) ** f3: ** vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma ** vlm.v\tv[0-9]+,0\([a-x0-9]+\) -** vsetvli\tzero,4,e32,m1,tu,mu +** vsetivli\tzero,4,e32,m1,tu,mu ** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) ** vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t ** vse32.v\tv[0-9]+,0\([a-x0-9]+\) @@ -58,7 +58,7 @@ void f3 (float * in, float *out) /* ** f4: -** vsetvli\tzero,4,e8,mf8,tu,ma +** vsetivli\tzero,4,e8,mf8,tu,ma ** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) ** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) ** vse8\.v\tv[0-9]+,0\([a-x0-9]+\) @@ -75,7 +75,7 @@ void f4 (int8_t * in, int8_t *out) ** f5: ** vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma ** vlm.v\tv[0-9]+,0\([a-x0-9]+\) -** vsetvli\tzero,4,e8,mf8,ta,ma +** vsetivli\tzero,4,e8,mf8,ta,ma ** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t ** vse8.v\tv[0-9]+,0\([a-x0-9]+\) ** ret @@ -93,7 +93,7 @@ void f5 (int8_t * in, int8_t *out) ** f6: ** vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma ** vlm.v\tv[0-9]+,0\([a-x0-9]+\) -** vsetvli\tzero,4,e8,mf8,tu,mu +** vsetivli\tzero,4,e8,mf8,tu,mu ** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) ** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t ** vse8.v\tv[0-9]+,0\([a-x0-9]+\) |