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| author | liuhongt <hongtao.liu@intel.com> | 2022-11-07 09:55:25 +0800 |
|---|---|---|
| committer | liuhongt <hongtao.liu@intel.com> | 2022-11-09 09:12:52 +0800 |
| commit | 916bec9a05ea522c81381e0c93590d46965d9c7b (patch) | |
| tree | abd62d69fe27dcf5226cfa27eedce2a068303d0a /gcc | |
| parent | 69023a9f955dbb6dddca5d270379193a124bdf3c (diff) | |
| download | gcc-916bec9a05ea522c81381e0c93590d46965d9c7b.zip gcc-916bec9a05ea522c81381e0c93590d46965d9c7b.tar.gz gcc-916bec9a05ea522c81381e0c93590d46965d9c7b.tar.bz2 | |
Fix incorrect insn type to avoid ICE in memory attr auto-detection.
Memory attribute auto detection will check operand 2 for type sselog,
and check operand 1 for type sselog1. For below 2 insns, there's no
operand 2. Change type to sselog1.
gcc/ChangeLog:
PR target/107540
* config/i386/sse.md (avx512f_movddup512<mask_name>): Change
type from sselog to sselog1.
(avx_movddup256<mask_name>): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr107540.c: New test.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/i386/sse.md | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/pr107540.c | 12 |
2 files changed, 14 insertions, 2 deletions
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 9a4fc01..de632b2 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -12203,7 +12203,7 @@ (const_int 6) (const_int 14)])))] "TARGET_AVX512F" "vmovddup\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}" - [(set_attr "type" "sselog") + [(set_attr "type" "sselog1") (set_attr "prefix" "evex") (set_attr "mode" "V8DF")]) @@ -12234,7 +12234,7 @@ (const_int 2) (const_int 6)])))] "TARGET_AVX && <mask_avx512vl_condition>" "vmovddup\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}" - [(set_attr "type" "sselog") + [(set_attr "type" "sselog1") (set_attr "prefix" "<mask_prefix>") (set_attr "mode" "V4DF")]) diff --git a/gcc/testsuite/gcc.target/i386/pr107540.c b/gcc/testsuite/gcc.target/i386/pr107540.c new file mode 100644 index 0000000..a0351ff --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr107540.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-flive-range-shrinkage -mavx" } */ + +typedef double __attribute__((__vector_size__ (32))) V; + +V v; + +void +foo (void) +{ + v = __builtin_ia32_movddup256 (v); +} |