rs6000.md (movdf_hardfloat32): Order alternatives consistently.

        * rs6000.md (movdf_hardfloat32): Order alternatives consistently.
        Use length of 4 not *.
        (movdf_hardfloat64): Same.  Support DFmode moves to/from CTR/LR.
        (movdf_softfloat64): Likewise.
        (movdi_internal32): Use length of 4 not *.
        (movti_power): Same.
        (ctrsi, ctrdi): Same.

From-SVN: r58299

2 files changed, 48 insertions, 34 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 89c32e9..6b48dde 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2002-10-18  David Edelsohn  <edelsohn@gnu.org>
+
+	* rs6000.md (movdf_hardfloat32): Order alternatives consistently.
+	Use length of 4 not *.
+	(movdf_hardfloat64): Same.  Support DFmode moves to/from CTR/LR.
+	(movdf_softfloat64): Likewise.
+	(movdi_internal32): Use length of 4 not *.
+	(movti_power): Same.
+	(ctrsi, ctrdi): Same.
+
 2002-10-18  Zack Weinberg  <zack@codesourcery.com>
 
 	* c-decl.c (start_decl): Point users of the old initialized-
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 66ceacf..749b881 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -8541,8 +8541,8 @@
 ;; The "??" is a kludge until we can figure out a more reasonable way
 ;; of handling these non-offsettable values.
 (define_insn "*movdf_hardfloat32"
-  [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,!r,!r,!r,f,f,m")
-	(match_operand:DF 1 "input_operand" "r,m,r,G,H,F,f,m,f"))]
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
+	(match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
   "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
    && (gpc_reg_operand (operands[0], DFmode)
        || gpc_reg_operand (operands[1], DFmode))"
@@ -8619,19 +8619,19 @@
 	  return \"\";
 	}
     case 3:
+      return \"fmr %0,%1\";
     case 4:
+      return \"lfd%U1%X1 %0,%1\";
     case 5:
-      return \"#\";
+      return \"stfd%U0%X0 %1,%0\";
     case 6:
-      return \"fmr %0,%1\";
     case 7:
-      return \"lfd%U1%X1 %0,%1\";
     case 8:
-      return \"stfd%U0%X0 %1,%0\";
+      return \"#\";
     }
 }"
-  [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore")
-   (set_attr "length" "8,16,16,8,12,16,*,*,*")])
+  [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*")
+   (set_attr "length" "8,16,16,4,4,4,8,12,16")])
 
 (define_insn "*movdf_softfloat32"
   [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
@@ -8675,8 +8675,8 @@
    (set_attr "length" "8,8,8,8,12,16")])
 
 (define_insn "*movdf_hardfloat64"
-  [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,!r,!r,!r,f,f,m")
-	(match_operand:DF 1 "input_operand" "r,m,r,G,H,F,f,m,f"))]
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!cl,!r,!r,!r,!r")
+	(match_operand:DF 1 "input_operand" "r,m,r,f,m,f,r,h,G,H,F"))]
   "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
    && (gpc_reg_operand (operands[0], DFmode)
        || gpc_reg_operand (operands[1], DFmode))"
@@ -8684,30 +8684,34 @@
    mr %0,%1
    ld%U1%X1 %0,%1
    std%U0%X0 %1,%0
-   #
-   #
-   #
    fmr %0,%1
    lfd%U1%X1 %0,%1
-   stfd%U0%X0 %1,%0"
-  [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore")
-   (set_attr "length" "4,4,4,8,12,16,4,4,4")])
+   stfd%U0%X0 %1,%0
+   mt%0 %1
+   mf%1 %0
+   #
+   #
+   #"
+  [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,*,*,*")
+   (set_attr "length" "4,4,4,4,4,4,4,4,8,12,16")])
 
 (define_insn "*movdf_softfloat64"
-  [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
-	(match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r")
+	(match_operand:DF 1 "input_operand" "r,r,h,m,r,G,H,F"))]
   "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
    && (gpc_reg_operand (operands[0], DFmode)
        || gpc_reg_operand (operands[1], DFmode))"
   "@
    mr %0,%1
+   mt%0 %1
+   mf%1 %0
    ld%U1%X1 %0,%1
    std%U0%X0 %1,%0
    #
    #
    #"
-  [(set_attr "type" "*,load,store,*,*,*")
-   (set_attr "length" "*,*,*,8,12,16")])
+  [(set_attr "type" "*,*,*,load,store,*,*,*")
+   (set_attr "length" "4,4,4,4,4,8,12,16")])
 
 (define_expand "movtf"
   [(set (match_operand:TF 0 "general_operand" "")
@@ -9026,7 +9030,7 @@
     }
 }"
   [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*,*,*")
-   (set_attr "length" "8,8,8,*,*,*,8,12,8,12,16")])
+   (set_attr "length" "8,8,8,4,4,4,8,12,8,12,16")])
 
 (define_split
   [(set (match_operand:DI 0 "gpc_reg_operand" "")
@@ -9241,7 +9245,7 @@
     }
 }"
   [(set_attr "type" "store,store,*,load,load")
-   (set_attr "length" "*,16,16,*,16")])
+   (set_attr "length" "4,16,16,4,16")])
 
 (define_insn "*movti_string"
   [(set (match_operand:TI 0 "reg_or_mem_operand" "=m,????r,????r")
@@ -14153,7 +14157,7 @@
     return \"bdz $+8\;b %l0\";
 }"
   [(set_attr "type" "branch")
-   (set_attr "length" "*,12,16")])
+   (set_attr "length" "4,12,16")])
 
 (define_insn "*ctrsi_internal2"
   [(set (pc)
@@ -14177,7 +14181,7 @@
     return \"{bdn|bdnz} $+8\;b %l0\";
 }"
   [(set_attr "type" "branch")
-   (set_attr "length" "*,12,16")])
+   (set_attr "length" "4,12,16")])
 
 (define_insn "*ctrdi_internal1"
   [(set (pc)
@@ -14201,7 +14205,7 @@
     return \"bdz $+8\;b %l0\";
 }"
   [(set_attr "type" "branch")
-   (set_attr "length" "*,12,16")])
+   (set_attr "length" "4,12,16")])
 
 (define_insn "*ctrdi_internal2"
   [(set (pc)
@@ -14225,7 +14229,7 @@
     return \"{bdn|bdnz} $+8\;b %l0\";
 }"
   [(set_attr "type" "branch")
-   (set_attr "length" "*,12,16")])
+   (set_attr "length" "4,12,16")])
 
 ;; Similar, but we can use GE since we have a REG_NONNEG.
 
@@ -14251,7 +14255,7 @@
     return \"bdz $+8\;b %l0\";
 }"
   [(set_attr "type" "branch")
-   (set_attr "length" "*,12,16")])
+   (set_attr "length" "4,12,16")])
 
 (define_insn "*ctrsi_internal4"
   [(set (pc)
@@ -14275,7 +14279,7 @@
     return \"{bdn|bdnz} $+8\;b %l0\";
 }"
   [(set_attr "type" "branch")
-   (set_attr "length" "*,12,16")])
+   (set_attr "length" "4,12,16")])
 
 (define_insn "*ctrdi_internal3"
   [(set (pc)
@@ -14299,7 +14303,7 @@
     return \"bdz $+8\;b %l0\";
 }"
   [(set_attr "type" "branch")
-   (set_attr "length" "*,12,16")])
+   (set_attr "length" "4,12,16")])
 
 (define_insn "*ctrdi_internal4"
   [(set (pc)
@@ -14323,7 +14327,7 @@
     return \"{bdn|bdnz} $+8\;b %l0\";
 }"
   [(set_attr "type" "branch")
-   (set_attr "length" "*,12,16")])
+   (set_attr "length" "4,12,16")])
 
 ;; Similar but use EQ
 
@@ -14349,7 +14353,7 @@
     return \"{bdn|bdnz} $+8\;b %l0\";
 }"
   [(set_attr "type" "branch")
-   (set_attr "length" "*,12,16")])
+   (set_attr "length" "4,12,16")])
 
 (define_insn "*ctrsi_internal6"
   [(set (pc)
@@ -14373,7 +14377,7 @@
     return \"bdz $+8\;b %l0\";
 }"
   [(set_attr "type" "branch")
-   (set_attr "length" "*,12,16")])
+   (set_attr "length" "4,12,16")])
 
 (define_insn "*ctrdi_internal5"
   [(set (pc)
@@ -14397,7 +14401,7 @@
     return \"{bdn|bdnz} $+8\;b %l0\";
 }"
   [(set_attr "type" "branch")
-   (set_attr "length" "*,12,16")])
+   (set_attr "length" "4,12,16")])
 
 (define_insn "*ctrdi_internal6"
   [(set (pc)
@@ -14421,7 +14425,7 @@
     return \"bdz $+8\;b %l0\";
 }"
   [(set_attr "type" "branch")
-   (set_attr "length" "*,12,16")])
+   (set_attr "length" "4,12,16")])
 
 ;; Now the splitters if we could not allocate the CTR register