diff options
| author | Peter Bergner <bergner@vnet.ibm.com> | 2016-11-23 20:07:51 -0600 |
|---|---|---|
| committer | Peter Bergner <bergner@gcc.gnu.org> | 2016-11-23 20:07:51 -0600 |
| commit | 90b725f0b08694778e4a10c45008d244342998d2 (patch) | |
| tree | e991ad6bd801ab49453f588872d64804afbe08da /gcc | |
| parent | 890a4eb0560520fe2093aef9b62067b7ee8816c7 (diff) | |
| download | gcc-90b725f0b08694778e4a10c45008d244342998d2.zip gcc-90b725f0b08694778e4a10c45008d244342998d2.tar.gz gcc-90b725f0b08694778e4a10c45008d244342998d2.tar.bz2 | |
re PR target/78458 (LRA ICE building libgcc for powerpc-linux-gnuspe e500v2)
gcc/
PR target/78458
* config/rs6000/rs6000.h (HARD_REGNO_CALLER_SAVE_MODE): Return MODE
if it is at least NREGS wide.
gcc/testsuite/
PR target/78458
* gcc.target/powerpc/pr78458.c: New.
From-SVN: r242818
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.h | 8 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/powerpc/pr78458.c | 15 |
4 files changed, 31 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ca575bc..71ce3f6 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2016-11-23 Peter Bergner <bergner@vnet.ibm.com> + + PR target/78458 + * config/rs6000/rs6000.h (HARD_REGNO_CALLER_SAVE_MODE): Return MODE + if it is at least NREGS wide. + 2016-11-23 Joseph Myers <joseph@codesourcery.com> * config/rs6000/rs6000.c (rs6000_legitimate_offset_address_p): For diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 19a476b..d1e36d9 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -1279,9 +1279,11 @@ enum data_align { align_abi, align_opt, align_both }; enough space to account for vectors in FP regs. However, TFmode/TDmode should not use VSX instructions to do a caller save. */ #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ - (TARGET_VSX \ - && ((MODE) == VOIDmode || ALTIVEC_OR_VSX_VECTOR_MODE (MODE)) \ - && FP_REGNO_P (REGNO) \ + ((NREGS) <= rs6000_hard_regno_nregs[MODE][REGNO] \ + ? (MODE) \ + : TARGET_VSX \ + && ((MODE) == VOIDmode || ALTIVEC_OR_VSX_VECTOR_MODE (MODE)) \ + && FP_REGNO_P (REGNO) \ ? V2DFmode \ : TARGET_E500_DOUBLE && (MODE) == SImode \ ? SImode \ diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 0af543c..831ca5e 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2016-11-23 Peter Bergner <bergner@vnet.ibm.com> + + PR target/78458 + * gcc.target/powerpc/pr78458.c: New. + 2016-11-23 Joseph Myers <joseph@codesourcery.com> * gcc.c-torture/compile/20161123-1.c: New test. diff --git a/gcc/testsuite/gcc.target/powerpc/pr78458.c b/gcc/testsuite/gcc.target/powerpc/pr78458.c new file mode 100644 index 0000000..777ac43 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr78458.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mcpu=8548 -mspe -mabi=spe -mlra" } */ +/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } } */ + +extern void bar (void); +long double +pr78458 (long double p1) +{ + bar (); + asm volatile ("# clobbers" ::: + "r14", "r15", "r16", "r17", "r18", "r19", + "r20", "r21", "r22", "r23", "r24", "r25", + "r26", "r27", "r28", "r29", "r30", "r31"); + return p1; +} |